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AT91SAM9G45B-CU-999

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34
SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
Figure 8-4. SAM9G45 Power Management Controller Block Diagram
8.7.1 Main Application Modes
The Power Management Controller provides 3 main application modes.
8.7.1.1 Normal Mode
z PLLA and UPLL are running respectively at 400 MHz and 480 MHz
z USB Device High Speed and Host EHCI High Speed operations are allowed
z Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
z System Input clock is PLLACK, PCK is 400 MHz
z MDIV is ‘11’, MCK is 133 MHz
z DDR2 can be used at up to 133 MHz
8.7.1.2 USB HS and LP-DDR Mode
z Only UPLL is running at 480 MHz, PLLA power consumption is saved
z USB Device High Speed and Host EHCI High Speed operations are allowed
z Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
z System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz
z MDIV is ‘01’, MCK is 120 MHz
z Only LP-DDR can be used at up to 120 MHz
8.7.1.3 No UDP HS, UHP FS and DDR2 Mode
z Only PLLA is running at 384 MHz, UPLL power consumption is saved
UHP48M
UHP12M
SysClk DDR
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,.../64
PCK
Processor
Clock
Controller
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
/1 /2 /3 /4
SLCK
MAINCK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
pck[..]
ON/OFF
UPLLCK
/1,/2
UPLLCK
USB
OHCI
USBDIV+1
/4
USB
EHCI
USBS
Divider
X /1 /1.5 /2
35
SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
z USB Device High Speed and Host EHCI High Speed operations are NOT allowed
z Full Speed OHCI input clock is PLLACK, USBDIV is 7 (division by 8)
z System Input clock is PLLACK, PCK is 384 MHz
z MDIV is ‘11’, MCK is 128 MHz
z DDR2 can be used at up to 128 MHz
8.8 Periodic Interval Timer
z Includes a 20-bit Periodic Counter, with less than 1μs accuracy
z Includes a 12-bit Interval Overlay Counter
z Real Time OS or Linux/WinCE compliant tick generator
8.9 Watchdog Timer
z 16-bit key-protected only-once-Programmable Counter
z Windowed, prevents the processor to be in a dead-lock on the watchdog access
8.10 Real-Time Timer
z Real-Time Timer, allowing backup of time with different accuracies
z 32-bit Free-running back-up Counter
z Integrates a 16-bit programmable prescaler running on slow clock
z Alarm Register capable to generate a wake-up of the system through the Shut Down Controller
8.11 Real Time Clock
z Low power consumption
z Full asynchronous design
z Two hundred year calendar
z Programmable Periodic Interrupt
z Alarm and update parallel load
z Control of alarm and update Time/Calendar Data In
8.12 General-Purpose Backup Registers
z Four 32-bit backup general-purpose registers
8.13 Advanced Interrupt Controller
z Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
z Thirty-two individually maskable and vectored interrupt sources
z Source 0 is reserved for the Fast Interrupt Input (FIQ)
z Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
z Programmable Edge-triggered or Level-sensitive Internal Sources
z Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
z One External Sources plus the Fast Interrupt signal
z 8-level Priority Controller
z Drives the Normal Interrupt of the processor
z Handles priority of the interrupt sources 1 to 31
z Higher priority interrupts can be served during service of lower priority interrupt
z Vectoring
z Optimizes Interrupt Service Routine Branch and Execution
36
SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
z One 32-bit Vector Register per interrupt source
z Interrupt Vector Register reads the corresponding current Interrupt Vector
z Protect Mode
z Easy debugging by preventing automatic operations when protect modes are enabled
z Fast Forcing
z Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
8.14 Debug Unit
z Composed of two functions
z Two-pin UART
z Debug Communication Channel (DCC) support
z Two-pin UART
z Implemented features are 100% compatible with the standard Atmel USART
z Independent receiver and transmitter with a common programmable Baud Rate Generator
z Even, Odd, Mark or Space Parity Generation
z Parity, Framing and Overrun Error Detection
z Automatic Echo, Local Loopback and Remote Loopback Channel Modes
z Support for two PDC channels with connection to receiver and transmitter
z Debug Communication Channel Support
z Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE
Interface
8.15 Chip Identification
The SAM9G45 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip ID Extension Register.
z Chip ID: 0x819B05A2
z Ext ID: 0x00000004
z JTAG ID: 05B2_703F
z ARM926 TAP ID: 0x0792603F
8.16 PIO Controllers
z 5 PIO Controllers, PIOA, PIOB, PIOC, PIOD and PIOE, controlling a maximum of 160 I/O Lines
z Each PIO Controller controls up to 32 programmable I/O Lines
z PIOA has 32 I/O Lines
z PIOB has 32 I/O Lines
z PIOC has 32 I/O Lines
z PIOD has 32 I/O Lines
z PIOE has 32 I/O Lines
z Fully programmable through Set/Clear Registers
z Multiplexing of two peripheral functions per I/O Line
z For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
z Input change interrupt
z Glitch filter
z Multi-drive option enables driving in open drain
z Programmable pull up on each I/O line
z Pin data status register, supplies visibility of the level on the pin at any time
z Synchronous output, provides Set and Clear of several I/O lines in a single write
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AT91SAM9G45B-CU-999

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IC MCU 32BIT 64KB ROM 324TFBGA SAM9G
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