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SC16C852VIET,115

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 25 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3 = 0)
In this mode, Transmit Ready (TXRDY
) will go to a logic 0 whenever the FIFO (THR, if
FIFO is not enabled) is empty. Receive Ready (RXRDY
) will go to a logic 0 whenever the
Receive Holding Register (RHR) is loaded with a character.
7.3.1.2 Mode 1 (FCR bit 3 = 1)
In this mode, the transmit ready (TXRDY
) is set when the transmit FIFO is below the
programmed trigger level. The receive ready (RXRDY
) is set when the receive FIFO fills
to the programmed trigger level. However, the FIFO continues to fill regardless of the
programmed level until the FIFO is full. RXRDY
remains a logic 0 as long as the FIFO fill
level is above the programmed trigger level.
7.3.2 FIFO mode
Table 11. FIFO Control Register bits description
Bit Symbol Description
7:6 FCR[7:6] Receive trigger level in 32-byte FIFO mode.
[1]
These bits are used to set the trigger level for receive FIFO interrupt and flow
control. The SC16C852V will issue a receive ready interrupt when the
number of characters in the receive FIFO reaches the selected trigger level.
Refer to Table 12
.
5:4 FCR[5:4] Transmit trigger level in 32-byte FIFO mode.
[2]
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C852V will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table 13
.
3 FCR[3] DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C852V is in the non-FIFO
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO, the TXRDY
signal will be a logic 0. Once
active, the TXRDY
signal will go to a logic 1 after the first character is loaded
into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C852V is in non-FIFO
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is
at least one character in the receive FIFO, the RXRDY signal will be a
logic 0. Once active, the RXRDY
signal will go to a logic 1 when there are no
more characters in the receiver.
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 26 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[1] For 128-byte FIFO mode, refer to Section 7.16, Section 7.17, Section 7.18.
[2] For 128-byte FIFO mode, refer to Section 7.15
, Section 7.17, Section 7.18.
[1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “
FIFO operation”.
[1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “
FIFO operation”.
3
(cont.)
Transmit operation in mode ‘1’: When the SC16C852V is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY
signal will be a logic 1 when
the transmit FIFO is completely full, see Section 6.10 “DMA operation”. It will
be a logic 0 when the trigger level has been reached.
Receive operation in mode ‘1’: When the SC16C852V is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the RXRDY signal will go to a logic 0.
Once activated, it will go to a logic 1 after there are no more characters in the
FIFO.
2 FCR[2] XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
1 FCR[1] RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
0 FCR[0] FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
Table 12. RCVR trigger levels
FCR[7] FCR[6] RX FIFO trigger level in 32-byte FIFO mode
[1]
0 0 8 bytes
0 1 16 bytes
1 0 24 bytes
1 1 28 bytes
Table 13. TX FIFO trigger levels
FCR[5] FCR[4] TX FIFO trigger level in 32-byte FIFO mode
[1]
0 0 16 bytes
0 1 8 bytes
1 0 24 bytes
1 1 30 bytes
Table 11. FIFO Control Register bits description
…continued
Bit Symbol Description
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 27 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.4 Interrupt Status Register (ISR)
The SC16C852V provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits. Table 14 “
Interrupt source” shows the
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 14. Interrupt source
Priority
level
ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt
1 000110LSR (Receiver Line Status Register)
2 000100RXRDY (Received Data Ready)
2 001100RXRDY (Receive Data time-out)
3 000010TXRDY (Transmitter Holding
Register Empty)
4 000000MSR (Modem Status Register)
5 010000RXRDY (Received Xoff signal)/
Special character
6 100000CTS, RTS change of state
Table 15. Interrupt Status Register bits description
Bit Symbol Description
7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C852V mode.
logic 0 or cleared = default condition
5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
logic 0 or cleared = default condition
3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see Table 14
).
logic 0 or cleared = default condition
0 ISR[0] INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

SC16C852VIET,115

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Buy SC16C852VIET,115
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 1.8V 2CH UART 128B
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