SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 37 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.22 Advanced Feature Control Register 2 (AFCR2)
Table 34. Advanced Feature Control Register 2 bits description
Bit Symbol Description
7:6 AFCR2[7:6] reserved
5 AFCR2[5] RTSInvert. Invert RTS or DTR signal in auto 9-bit mode.
0 = RTS or DTR is set to 0 by the UART during transmission, and to 1
during reception
1 = RTS or DTR is set to 1 by the UART during transmission, and to 0
during reception
4 AFCR2[4] RTSCon. Enable the transmitter to control RTS or DTR signal in auto 9-bit
mode.
0 = transmitter does not control RTS or DTR signal
1 = transmitter controls RTS or DTR signal
3 AFCR2[3] RS485 RTS/DTR. Select RTSA
/RTSB or DTRA/DTRB pin to control the
external transceiver.
0 = RTSA/RTSB pin is used to control the external transceiver
1 = DTRA
/DTRB pin is used to control the external transceiver
2 AFCR2[2] TXDisable. Disable transmitter.
0 = transmitter is enabled
1 = transmitter is disabled
1 AFCR2[1] RXDisable. Disable receiver.
0 = receiver is enabled
1 = receiver is disabled
0 AFCR2[0] 9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode.
0 = normal RS-232 mode
1 = enable 9-bit mode
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 38 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.23 SC16C852V external reset condition and software reset
These two reset methods are identical and will reset the internal registers as indicated in
Table 35
.
Table 35. Reset state for registers
Register Reset state
IER IER[7:0] = 0
FCR FCR[7:0] = 0
ISR ISR[7:1] = 0; ISR[0] = 1
LCR LCR[7:0] = 0
MCR MCR[7:0] = 0
LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR MSR[7:4] = input signals; MSR[3:0] = 0
EFCR EFCR[7:0] = 0
SPR SPR[7:0] = 1
DLL undefined
DLM undefined
TXLVLCNT TXLVLCNT[7:0] = 0
RXLVLCNT RXLVLCNT[7:0] = 0
EFR EFR[7:0] = 0
Xon-1 Undefined
Xon-2 Undefined
Xoff-1 Undefined
Xoff-2 Undefined
TXINTLVL TXINTLVL[7:0] = 0
RXINTLVL RXINTLVL[7:0] = 0
FLWCNTH FLWCNTH[7:0] = 0
FLWCNTL FLWCNTL[7:0] = 0
CLKPRES CLKPRES[7:0] = 0
RS485TIME RS485TIME[7:0] = 0
AFCR2 AFCR2[7:0] = 0
AFCR1 AFCR1[7:0] = 0
Table 36. Reset state for outputs
Output Reset state
TXA, TXB logic 1
OP2A
, OP2B logic 1
RTSA
, RTSB logic 1
DTRA
, DTRB logic 1
INTA, INTB 3-state condition
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 39 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
8. Limiting values
[1] V
n
should not exceed 2.5 V.
9. Static characteristics
[1] Hysteresis input.
[2] Except XTAL2, V
OL
=1V typical.
[3] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode.
[4] Activate by LOWPWR pin.
Table 37. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage - 2.5 V
V
n
voltage on any other pin
[1]
V
SS
0.3 V
DD
+0.3 V
T
amb
ambient temperature operating in free air 40 +85 °C
T
stg
storage temperature 65 +150 °C
P
tot
/pack total power dissipation per
package
-500mW
Table 38. Static characteristics
T
amb
=
40
°
C to +85
°
C; V
DD
= 1.65 V to 1.95 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
IL(clk)
clock LOW-level input voltage XTAL1 pin - - 0.25 V
V
IH(clk)
clock HIGH-level input voltage XTAL1 pin 1.35 - - V
V
IL
LOW-level input voltage except X1 clock,
LOWPWR pin
--0.45V
LOWPWR pin
[1]
--0.45V
V
IH
HIGH-level input voltage except X1 clock,
LOWPWR pin
1.35 - - V
LOWPWR pin
[1]
1.35 - - V
V
OL
LOW-level output voltage I
OL
=2mA
[2]
--0.35V
V
OH
HIGH-level output voltage I
OH
= 800 μA 1.45--V
I
LIL
LOW-level input leakage
current
--1μA
I
LIH
HIGH-level input leakage
current
--1μA
I
L(clk)
clock leakage current LOW-level - - 30 μA
HIGH-level - - 30 μA
I
DD
supply current f = 5 MHz - - 2 mA
I
DD(sleep)
sleep mode supply current
[3]
--5μA
I
DD(lp)
low-power mode supply
current
[4]
--5μA
C
i
input capacitance - - 5 pF

SC16C852VIET,115

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 1.8V 2CH UART 128B
Lifecycle:
New from this manufacturer.
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