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SC16C852VIET,115

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 43 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Fig 14. Receive timing
D0 D1 D2 D3 D4 D5 D6 D7
active
active
16 baud rate clock
002aac35
8
RXA, RXB
INTA, INTB
IOR
t
d(IOR-INTL)
t
d(stop-INT)
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
start
bit
data bits (0 to 7)
next
data
start
bit
Fig 15. Receive ready timing in non-FIFO mode
D0 D1 D2 D3 D4 D5 D6 D7
002aac35
9
next
data
start
bit
stop
bit
parity
bit
t
d(stop-RXRDY)
RXA, RXB
RXRDYA
IOR
active data
ready
start
bit
data bits (0 to 7)
active
t
d(IOR-RXRDYH)
RXRDYB
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 44 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Fig 16. Receive ready timing in FIFO mode
D0 D1 D2 D3 D4 D5 D6 D7
002aac360
first byte that
reaches the
trigger level
stop
bit
parity
bit
t
d(stop-RXRDY)
RXA, RXB
RXRDYA
IOR
active data
ready
start
bit
data bits (0 to 7)
active
t
d(IOR-RXRDYH)
RXRDYB
Fig 17. Transmit timing
active
transmitter ready
active
16 baud rate clock
002aac36
1
t
d(IOW-INTL)
INTA, INTB
IOW
active
D0 D1 D2 D3 D4 D5 D6 D7
TXA, TXB
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
start
bit
data bits (0 to 7)
next
data
start
bit
t
d(start-INT)
t
d(IOW-TX)
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 45 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Fig 18. Transmit ready timing in non-FIFO mode
D0 D1 D2 D3 D4 D5 D6 D7
002aac36
2
stop
bit
parity
bit
t
d(IOW-TXRDYH)
TXA, TXB
IOW
AD0 to AD7
active transmitter
ready
start
bit
data bits (0 to 7)
next
data
start
bit
byte #1
TXRDYA
t
d(start-TXRDY)
transmitter
not ready
active
TXRDYB
Fig 19. Transmit ready timing in FIFO mode (DMA mode ‘1’)
D0 D1 D2 D3 D4 D5 D6 D7
002aac36
3
stop
bit
parity
bit
t
d(IOW-TXRDYH)
TXA, TXB
IOW
AD0 to AD7
start
bit
data bits (0 to 7)
byte #32 or
byte #128
TXRDYA
t
d(start-TXRDY)
FIFO full
active
5 data bits
6 data bits
7 data bits
TXRDYB
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

SC16C852VIET,115

Mfr. #:
Buy SC16C852VIET,115
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 1.8V 2CH UART 128B
Lifecycle:
New from this manufacturer.
Delivery:
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