SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 6 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
5.2 Pin description
Fig 5. TFBGA36 ball mapping (transparent top view)
AD4 AD2 AD0 RIA DSRA CTSA
123456
AD5 AD3 AD1 CDA RESET DTRB
A
B
AD7 RXB AD6 V
DD
DTRA RTSAC
RXA XTAL1 V
SS
INTA INTBD
TXB CS IOW DSRB RTSB LLAE
LOWPWR XTAL2 IOR RIB CTSBF
002aac35
TXA
CDB
Table 2. Pin description
Symbol Pin Type Description
TFBGA36 HVQFN48
AD0 A3 44 I/O Address and Data bus (bidirectional). These pins are the 8-bit multiplexed
data bus and address bus for transferring information to or from the controlling
CPU. AD0 is the least significant bit and is address A0 during the address
cycle, and AD7 is the most significant bit and is address A7 during the address
cycle.
AD1 B3 45 I/O
AD2 A2 46 I/O
AD3 B2 47 I/O
AD4 A1 48 I/O
AD5 B1 1 I/O
AD6 C3 2 I/O
AD7 C1 3 I/O
CDA
B4 40 I Carrier Detect (active LOW). These inputs are associated with individual
UART channels A through B. A logic 0 on this pin indicates that a carrier has
been detected by the modem for that channel.
CDB
F3 16 I
CS
E2 10 I Chip Select (active LOW). This pin enables the data transfers between the
host and the SC16C852V for the addressed channel. Individual channel
selection is done with address A6. When A6 is 0 channel A is selected, and
when A6 is 1 channel B is selected.
CTSA
A6 38 I Clear to Send (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on the CTS
pin indicates the modem or
data set is ready to accept transmit data from the SC16C852V. Status can be
tested by reading MSR[4].
CTSB
F6 23 I
DSRA
A5 39 I Data Set Ready (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates the modem or data
set is powered-on and is ready for data exchange with the UART. Status can be
tested by reading MSR[5].
DSRB
E4 20 I
DTRA
C5 34 O Data Terminal Ready (active LOW). These outputs are associated with
individual UART channels, A through B. A logic 0 on this pin indicates that the
SC16C852V is powered-on and ready. This pin can be controlled via the
Modem Control Register. Writing a logic 1 to MCR[0] will set the DTR
output to
logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to
MCR[0], or after a reset.
DTRB B6 35 O
