SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 40 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
10. Dynamic characteristics
[1] External clock only; maximum crystal frequency is 24 MHz.
[2] 10 % of the data bus fall or rise time.
[3] RCLK is an internal frequency and it is equal to 16 times the baud rate.
Table 39. Dynamic characteristics
T
amb
=
−
40
°
C to +85
°
C; V
DD
= 1.65 V to 1.95 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
XTAL1
frequency on pin XTAL1
[1]
--80MHz
t
d(CS-LLAH)
delay time from CS to LLA HIGH 10 - - ns
t
su(A-LLAH)
set-up time from address to LLA HIGH 5 - - ns
t
w(LLA)
LLA pulse width time 10 - - ns
t
h(LLAH-A)
address hold time after LLA HIGH 10 - - ns
t
d(IOW)
IOW delay time 10 - - ns
t
d(IOR-DV)
delay time from IOR to data valid 25 pF load - - 40 ns
t
w(IOR)
IOR pulse width time 20 - - ns
t
d(LLAH-IORL)
delay time from LLA HIGH to IOR LOW 10 - - ns
t
w(IOW)
IOW pulse width time 10 - - ns
t
h(IOWH-D)
data input hold time after IOW HIGH 5 - - ns
t
d(LLAH-IOWL)
delay time from LLA HIGH to IOW LOW 10 - - ns
t
su(D-IOWH)
set-up time from data input to IOW HIGH 5 - - ns
t
d(IOR)
IOR delay time 10 - - ns
t
dis(IOR-QZ)
disable time from IOR to high-impedance data
output
[2]
25 pF load - - 20 ns
t
d(IOW-Q)
delay time from IOW to data output 25 pF load - - 50 ns
t
d(modem-INT)
delay time from modem to INT 25 pF load - - 50 ns
t
d(IOR-INTL)
delay time from IOR to INT LOW 25 pF load - - 50 ns
t
WH
pulse width HIGH 6 - - ns
t
WL
pulse width LOW 6 - - ns
t
w(clk)
clock pulse width 12.5 - - ns
t
d(stop-INT)
delay time from stop to INT 25 pF load
[3]
--1T
RCLK
s
t
d(stop-RXRDY)
delay time from stop to RXRDY 25 pF load
[3]
--1T
RCLK
s
t
d(IOR-RXRDYH)
delay time from IOR to RXRDY HIGH 25 pF load - - 50 ns
t
d(start-INT)
delay time from start to INT 25 pF load - - 1T
RCLK
s
t
d(IOW-TX)
delay time from IOW to TX
[3]
8T
RCLK
- 24T
RCLK
s
t
d(IOW-INTL)
delay time from IOW to INT LOW 25 pF load - - 50 ns
t
d(IOW-TXRDYH)
delay time from IOW to TXRDY HIGH 25 pF load - - 50 ns
t
d(start-TXRDY)
delay time from start to TXRDY 25 pF load
[3]
--8T
RCLK
s
t
w(RESET_N)
pulse width on pin RESET 10 - - ns
