NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 January 2011
Document identifier: SC16C852V
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Functional description . . . . . . . . . . . . . . . . . . . 9
6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . . 9
6.2 Extended mode (128-byte FIFO) . . . . . . . . . . 10
6.3 Internal registers. . . . . . . . . . . . . . . . . . . . . . . 10
6.4 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11
6.4.1 32-byte FIFO mode . . . . . . . . . . . . . . . . . . . . 11
6.4.2 128-byte FIFO mode . . . . . . . . . . . . . . . . . . . 11
6.5 Hardware flow control. . . . . . . . . . . . . . . . . . . 11
6.6 Software flow control . . . . . . . . . . . . . . . . . . . 12
6.7 Special character detect . . . . . . . . . . . . . . . . . 13
6.8 Interrupt priority and time-out interrupts . . . . . 13
6.9 Programmable baud rate generator . . . . . . . . 14
6.10 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 16
6.11 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 16
6.12 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.12.1 Conditions to enter Sleep mode . . . . . . . . . . . 18
6.12.2 Conditions to resume normal operation . . . . . 18
6.13 Low power feature . . . . . . . . . . . . . . . . . . . . . 18
6.14 RS-485 features . . . . . . . . . . . . . . . . . . . . . . . 19
6.14.1 Auto RS-485 RTS
control . . . . . . . . . . . . . . . . 19
6.14.2 RS-485 RTS inversion . . . . . . . . . . . . . . . . . . 19
6.14.3 Auto 9-bit mode (RS-485). . . . . . . . . . . . . . . . 19
6.14.3.1 Normal Multi-drop mode. . . . . . . . . . . . . . . . . 19
6.14.3.2 Auto address detection. . . . . . . . . . . . . . . . . . 20
7 Register descriptions . . . . . . . . . . . . . . . . . . . 20
7.1 Transmit (THR) and Receive (RHR)
Holding Registers . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Interrupt Enable Register (IER) . . . . . . . . . . . 23
7.2.1 IER versus transmit/receive FIFO
interrupt mode operation . . . . . . . . . . . . . . . . 24
7.2.2 IER versus receive/transmit FIFO
polled mode operation . . . . . . . . . . . . . . . . . . 24
7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 25
7.3.1 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3.1.1 Mode 0 (FCR bit 3 = 0). . . . . . . . . . . . . . . . . . 25
7.3.1.2 Mode 1 (FCR bit 3 = 1). . . . . . . . . . . . . . . . . . 25
7.3.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 Interrupt Status Register (ISR) . . . . . . . . . . . . 27
7.5 Line Control Register (LCR) . . . . . . . . . . . . . . 28
7.6 Modem Control Register (MCR) . . . . . . . . . . . 29
7.7 Line Status Register (LSR) . . . . . . . . . . . . . . 30
7.8 Modem Status Register (MSR) . . . . . . . . . . . 31
7.9 Extra Feature Control Register (EFCR). . . . . 32
7.10 Scratchpad Register (SPR) . . . . . . . . . . . . . . 32
7.11 Division Latch (DLL and DLM). . . . . . . . . . . . 32
7.12 Transmit FIFO Level Count (TXLVLCNT) . . . 32
7.13 Receive FIFO Level Count (RXLVLCNT). . . . 32
7.14 Enhanced Feature Register (EFR) . . . . . . . . 33
7.15 Transmit Interrupt Level register (TXINTLVL) 34
7.16 Receive Interrupt Level register (RXINTLVL). 34
7.17 Flow Control Trigger Level High (FLWCNTH) 35
7.18 Flow Control Trigger Level Low (FLWCNTL) . 35
7.19 Clock prescaler (CLKPRES) . . . . . . . . . . . . . 35
7.20 RS-485 turn-around time delay (RS485TIME) 36
7.21 Advanced Feature Control Register 1
(AFCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.22 Advanced Feature Control Register 2
(AFCR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.23 SC16C852V external reset condition and
software reset . . . . . . . . . . . . . . . . . . . . . . . . 38
8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 39
9 Static characteristics . . . . . . . . . . . . . . . . . . . 39
10 Dynamic characteristics. . . . . . . . . . . . . . . . . 40
10.1 Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 41
11 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 47
12 Soldering of SMD packages. . . . . . . . . . . . . . 49
12.1 Introduction to soldering. . . . . . . . . . . . . . . . . 49
12.2 Wave and reflow soldering. . . . . . . . . . . . . . . 49
12.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 49
12.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 50
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 52
15 Legal information . . . . . . . . . . . . . . . . . . . . . . 53
15.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 53
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 53
15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 54
16 Contact information . . . . . . . . . . . . . . . . . . . . 54
17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
