SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 7 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
INTA D5 30 O Channel A interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTA is set to the active mode when MCR[3] is
set to a logic 1. INTA is set to the 3-state mode when MCR[3] is set to a logic 0.
See Table 21
.
INTB D6 29 O Channel B interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTB is set to the active mode when MCR[3] is
set to a logic 1. INTB is set to the 3-state mode when MCR[3] is set to a logic 0.
See Table 21
.
IOR
F4 19 I Read strobe (active LOW). A HIGH to LOW transition on this signal starts the
read cycle. The SC16C852V reads a byte from the internal register and puts
the byte on the data bus for the host to retrieve.
IOW
E3 15 I Write strobe (active LOW). A HIGH to LOW transition on this signal starts the
write cycle, and a LOW to HIGH transition transfers the data on the data bus to
the internal register.
LLA
E6 28 I Latch Lower Address (active LOW). A logic LOW on this pin puts the VLIO
interface in the address phase of the transaction, where the lower 8 bits of the
VLIO (specifying the UART register and the channel address) are loaded into
the address latch of the device through the AD7 to AD0 bus. A logic HIGH puts
the VLIO interface in the data phase where data can are transferred between
the host and the UART.
LOWPWR F1 12 I Low Power. When asserted (active HIGH), the device immediately goes into
low power mode. The oscillator is shut-off and some host interface pins are
isolated from the host’s bus to reduce power consumption. The device only
returns to normal mode when the LOWPWR pin is de-asserted. On the
negative edge of a de-asserting LOWPWR signal, the device is automatically
reset and all registers return to their default reset states. This pin has an
internal pull-down resistor, therefore, it can be left unconnected.
n.c. - 11, 24, 25,
26, 27, 37
- not connected
OP2A
-32OOutput 2 (user-defined). This function is associated with individual channels,
A through B. The state at these pin(s) are defined by the user and through
MCR register bit 3. INTA, INTB are set to the active mode and OP2A
/OP2B to
logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the 3-state mode
and OP2A/OP2B to a logic 1 when MCR[3] is set to a logic 0 (see Table 20
“Modem Control Register bits description”, bit 3). Since these bits control both
the INTA, INTB operation and OP2A
/OP2B outputs, only one function should
be used at one time, interrupt or OP
function.
OP2B
-9O
RESET
B5 36 I Master reset (active LOW). A reset pulse will reset the internal registers and
all the outputs. The SC16C852V transmitter outputs and receiver inputs will be
disabled during reset time. (See Section 7.23 “
SC16C852V external reset
condition and software reset” for initialization details.)
RIA
A4 41 I Ring Indicator (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates the modem has
received a ringing signal from the telephone line. A logic 1 transition on this
input pin will generate an interrupt.
RIB
F5 21 I
RTSA
C6 33 O Request to Send (active LOW). These outputs are associated with individual
UART channels, A through B. A logic 0 on the RTS
pin indicates the transmitter
has data ready and waiting to send. Writing a logic 1 in the modem control
register MCR[1] will set this pin to a logic 0, indicating data is available. After a
reset this pin will be set to a logic 1.
RTSB E5 22 O
Table 2. Pin description
…continued
Symbol Pin Type Description
TFBGA36 HVQFN48
