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SC16C852VIET,115

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 46 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Fig 20. Infrared transmit timing
Fig 21. Infrared receive timing
01010011 10
UART frame
TX data
1
/
2
bit time
002aaa21
2
data bitsstart stop
bit
time
IrDA TX data
3
/
16
bit time
01010011 10
UART frame
RX data
IrDA RX data
bit
time
002aaa21
3
start data bits stop
0 to 1 16× clock delay
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 47 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
11. Package outline
Fig 22. Package outline SOT778-3 (HVQFN48)
terminal 1
index area
terminal 1
index area
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
SOT778-3 - - -
- - -
- - -
SOT778-
3
04-06-16
04-06-23
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included
DIMENSIONS (mm are the original dimensions)
H
VQFN48: plastic thermal enhanced very thin quad flat package; no leads;
4
8 terminals; body 6 x 6 x 0.85 mm
detail X
E
h
D
h
L
A
c
A
1
b
D
E
B
C
A
12
13 24
48 37
1
25
36
e
2
e
1
e
e
1/2 e
1/2 e
AC
B
v
M
Cw
M
y
C
y
1
X
0 2.5 5 mm
scale
UNIT
mm
0.05
0.00
0.25
0.15
6.1
5.9
6.1
5.9
3.95
3.65
0.5
0.3
A
1
b
1
A
(1)
max
D
(1)
E
(1)
E
h
3.95
3.65
D
h
ee
1
L v
0.14.4
e
2
4.40.4
c
0.2
w
0.05
y
0.05
y
1
0.1
SC16C852V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 21 January 2011 48 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Fig 23. Package outline SOT912-1 (TFBGA36)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
SOT912-1
SOT912-
1
05-08-09
05-09-01
UNIT
A
max
mm 1.15
0.25
0.15
0.90
0.75
0.35
0.25
3.6
3.4
3.6
3.4
A
1
DIMENSIONS (mm are the original dimensions)
T
FBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm
0 2.5 5 mm
scale
A
2
b D E e
2
2.5
e
0.5
e
1
2.5
y
1
0.1
v
0.15
w
0.05
y
0.08
- - - - - -- - -
b
e
2
e
1
e
e
1/2 e
1/2 e
AC
B
v
M
Cw
M
ball A1
index area
A
B
C
D
E
F
246135
ball A1
index area
B A
E
D
C
y
C
y
1
X
detail X
A
1
A
2
A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

SC16C852VIET,115

Mfr. #:
Buy SC16C852VIET,115
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 1.8V 2CH UART 128B
Lifecycle:
New from this manufacturer.
Delivery:
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