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5M160ZM68I5N

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Chapter 3: DC and Switching Characteristics for MAX V Devices 3–19
Timing Model and Specifications
May 2011 Altera Corporation MAX V Device Handbook
External Timing Parameters
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in Table 3–32 on page 3–23 through Table 3–36 on page 3–25.
f For more information about each external timing parameters symbol, refer to
AN629: Understanding Timing in Altera CPLDs.
Figure 3–5. UFM Erase Waveform
ARShft
ARClk
ARDin
DRShft
DRClk
DRDin
DRDout
Program
Erase
Busy
9 Address Bits
t
ASU
t
ACLK
t
AH
t
ADH
t
ADS
t
EB
t
EPMX
t
OSCS
t
OSCH
OSC_ENA
t
BE
Table 3–25. Routing Delay Internal Timing Microparameters for MAX V Devices
Routing
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
Unit
C4 C5, I5 C4 C5, I5
Min Max Min Max Min Max Min Max
t
C4
— 860 — 1,973 — 561 — 690 ps
t
R4
— 655 — 1,479 — 445 — 548 ps
t
LOCAL
— 1,143 — 2,947 — 731 — 899 ps
3–20 Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
MAX V Device Handbook May 2011 Altera Corporation
Table 3–26 lists the external I/O timing parameters for the 5M40Z, 5M80Z, 5M160Z,
and 5M240Z devices.
Table 3–27 lists the external I/O timing parameters for the T144 package of the
5M240Z device.
Table 3–26. Global Clock External I/O Timing Parameters for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z Devices
(Note 1 ), (2)
Symbol Parameter Condition
C4 C5, I5
Unit
Min Max Min Max
t
PD1
Worst case pin-to-pin delay through one LUT 10 pF — 7.9 — 14.0 ns
t
PD2
Best case pin-to-pin delay through one LUT 10 pF — 5.8 — 8.5 ns
t
SU
Global clock setup time — 2.4 — 4.6 — ns
t
H
Global clock hold time — 0 — 0 — ns
t
CO
Global clock to output delay 10 pF 2.0 6.6 2.0 8.6 ns
t
CH
Global clock high time — 253 — 339 — ps
t
CL
Global clock low time — 253 — 339 — ps
t
CNT
Minimum global clock period for
16-bit counter
— 5.4 — 8.4 — ns
f
CNT
Maximum global clock frequency for 16-bit
counter
— — 184.1 — 118.3 MHz
Notes to Table 3–26:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
(2) Not applicable to the T144 package of the 5M240Z device.
Table 3–27. Global Clock External I/O Timing Parameters for the 5M240Z Device (Note 1), (2)
Symbol Parameter Condition
C4 C5, I5
Unit
Min Max Min Max
t
PD1
Worst case pin-to-pin delay through one LUT 10 pF — 9.5 — 17.7 ns
t
PD2
Best case pin-to-pin delay through one LUT 10 pF — 5.7 — 8.5 ns
t
SU
Global clock setup time — 2.2 — 4.4 — ns
t
H
Global clock hold time — 0 — 0 — ns
t
CO
Global clock to output delay 10 pF 2.0 6.7 2.0 8.7 ns
t
CH
Global clock high time — 253 — 339 — ps
t
CL
Global clock low time — 253 — 339 — ps
t
CNT
Minimum global clock period for 16-bit
counter
— 5.4 — 8.4 — ns
f
CNT
Maximum global clock frequency for 16-bit
counter
— — 184.1 — 118.3 MHz
Notes to Table 3–27:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
(2) Only applicable to the T144 package of the 5M240Z device.
Chapter 3: DC and Switching Characteristics for MAX V Devices 3–21
Timing Model and Specifications
May 2011 Altera Corporation MAX V Device Handbook
Table 3–28 lists the external I/O timing parameters for the 5M570Z device.
Table 3–29 lists the external I/O timing parameters for the 5M1270Z device.
Table 3–28. Global Clock External I/O Timing Parameters for the 5M570Z Device (Note 1)
Symbol Parameter Condition
C4 C5, I5
Unit
Min Max Min Max
t
PD1
Worst case pin-to-pin delay through one LUT 10 pF — 9.5 — 17.7 ns
t
PD2
Best case pin-to-pin delay through one LUT 10 pF — 5.7 — 8.5 ns
t
SU
Global clock setup time — 2.2 — 4.4 — ns
t
H
Global clock hold time — 0 — 0 — ns
t
CO
Global clock to output delay 10 pF 2.0 6.7 2.0 8.7 ns
t
CH
Global clock high time — 253 — 339 — ps
t
CL
Global clock low time — 253 — 339 — ps
t
CNT
Minimum global clock period for 16-bit
counter
— 5.4 — 8.4 — ns
f
CNT
Maximum global clock frequency for 16-bit
counter
— — 184.1 — 118.3 MHz
Note to Table 3–28:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
Table 3–29. Global Clock External I/O Timing Parameters for the 5M1270Z Device (Note 1), (2)
Symbol Parameter Condition
C4 C5, I5
Unit
Min Max Min Max
t
PD1
Worst case pin-to-pin delay through one LUT 10 pF — 8.1 — 10.0 ns
t
PD2
Best case pin-to-pin delay through one LUT 10 pF — 4.8 — 5.9 ns
t
SU
Global clock setup time — 1.5 — 1.9 — ns
t
H
Global clock hold time — 0 — 0 — ns
t
CO
Global clock to output delay 10 pF 2.0 5.9 2.0 7.3 ns
t
CH
Global clock high time — 216 — 266 — ps
t
CL
Global clock low time — 216 — 266 — ps
t
CNT
Minimum global clock period for 16-bit
counter
— 4.0 — 5.0 — ns
f
CNT
Maximum global clock frequency for 16-bit
counter
— — 247.5 — 201.1 MHz
Notes to Table 3–29:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
(2) Not applicable to the F324 package of the 5M1270Z device.
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5M160ZM68I5N

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Intel / Altera
Description:
CPLD - Complex Programmable Logic Devices CPLD - MAX V 128 Macro 52 IOs
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