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5M160ZM68I5N

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3–28 Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
MAX V Device Handbook May 2011 Altera Corporation
Tabl e 3 –4 0 lists the emulated RSDS output timing specifications for MAX V devices.
Table 3–40. Emulated RSDS Output Timing Specifications for MAX V Devices
Parameter Mode
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z/5M1270Z/
5M2210Z
Unit
C4, C5, I5
Min Max
Data rate (1)
10 — 200 Mbps
9 — 200 Mbps
8 — 200 Mbps
7 — 200 Mbps
6 — 200 Mbps
5 — 200 Mbps
4 — 200 Mbps
3 — 200 Mbps
2 — 200 Mbps
1 — 200 Mbps
t
DUTY
—4555%
Total jitter (2) ——0.2UI
t
RISE
——450ps
t
FALL
——450ps
Notes to Table 3–40:
(1) For the input clock pin to achieve 200 Mbps, use I/O standard with V
CCIO
of 1.8 V and above.
(2) This specification is based on external clean clock source.
Chapter 3: DC and Switching Characteristics for MAX V Devices 3–29
Timing Model and Specifications
May 2011 Altera Corporation MAX V Device Handbook
JTAG Timing Specifications
Figure 3–6 shows the timing waveform for the JTAG signals for the MAX V device
family.
Tabl e 3 –4 1 lists the JTAG timing parameters and values for the MAX V device family.
Figure 3–6. JTAG Timing Waveform for MAX V Devices
TDI
TMS
TDO
TCK
Signal
to be
Captured
Signal
to be
Driven
t
JCP
t
JCH
t
JCL
t
JPSU
t
JPH
t
JPCO
t
JPXZ
t
JPZX
t
JSSU
t
JSH
t
JSZX
t
JSCO
t
JSXZ
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 1 of 2)
Symbol Parameter Min Max Unit
t
JCP
(1)
TCK
clock period for V
CCIO1
= 3.3 V 55.5 — ns
TCK
clock period for V
CCIO1
= 2.5 V 62.5 — ns
TCK
clock period for V
CCIO1
= 1.8 V 100 — ns
TCK
clock period for V
CCIO1
= 1.5 V 143 — ns
t
JCH
TCK
clock high time 20 — ns
t
JCL
TCK
clock low time 20 — ns
t
JPSU
JTAG port setup time (2) 8—ns
t
JPH
JTAG port hold time 10 — ns
t
JPCO
JTAG port clock to output (2) —15ns
t
JPZX
JTAG port high impedance to valid output (2) —15ns
t
JPXZ
JTAG port valid output to high impedance (2) —15ns
t
JSSU
Capture register setup time 8 — ns
t
JSH
Capture register hold time 10 — ns
t
JSCO
Update register clock to output — 25 ns
t
JSZX
Update register high impedance to valid output — 25 ns
3–30 Chapter 3: DC and Switching Characteristics for MAX V Devices
Document Revision History
MAX V Device Handbook May 2011 Altera Corporation
Document Revision History
Tabl e 3 –4 2 lists the revision history for this chapter.
t
JSXZ
Update register valid output to high impedance — 25 ns
Notes to Table 3–41:
(1) Minimum clock period specified for 10 pF load on the
TDO
pin. Larger loads on
TDO
degrades the maximum
TCK
frequency.
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and
1.5-V LVCMOS operation, the t
JPSU
minimum is 6 ns and t
JPCO
, t
JPZX
, and t
JPXZ
are maximum values at 35 ns.
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)
Symbol Parameter Min Max Unit
Table 3–42. Document Revision History
Date Version Changes
May 2011 1.2 Updated Table 3–2, Table 3–15, Table 3–16, and Table 3–33.
January 2011 1.1 Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40.
December 2010 1.0 Initial release.
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5M160ZM68I5N

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Intel / Altera
Description:
CPLD - Complex Programmable Logic Devices CPLD - MAX V 128 Macro 52 IOs
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