ZL30116GGG2V2 Datasheet ZL30116GGG2V2, ZL30116GGGV2 | P1-P3

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

• Supports the requirements of Telcordia GR-253 and

GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and

the requirements of ITU-T G.781 SETS, G.813

SEC, G.823, G.824 and G.825 clocks

• Internal APLL provides standard output clock

frequencies up to 622.08 MHz that meet jitter

requirements for interfaces up to OC-192/STM-64

• Programmable output synthesizers generate clock

frequencies from any multiple of 8 kHz up to

77.76 MHz in addition to 2 kHz

• Provides two DPLLs which are independently

configurable through a serial software interface

• DPLL1 provides all the features necessary for

generating SONET/SDH compliant clocks including

automatic hitless reference switching, automatic

mode selection (locked, free-run, holdover),

selectable loop bandwidth and pull-in range

• DPLL2 provides a comprehensive set of features

necessary for generating derived output clocks and

other general purpose clocks

• Provides 8 reference inputs which support clock

frequencies with any multiples of 8 kHz up to

77.76 MHz in addition to 2 kHz

• Supports master/slave configuration for

AdvancedTCA

• Configurable input to output delay and output to

output phase alignment

• Optional external feedback path provides dynamic

input to output delay compensation

• Provides 3 sync inputs for output frame pulse

alignment

• Generates several styles of output frame pulses

with selectable pulse width, polarity and frequency

• Flexible input reference monitoring automatically

disqualifies references based on frequency and

phase irregularities

• Supports IEEE 1149.1 JTAG Boundary Scan

June 2008

Figure 1 - Block Diagram

dpll1_mod_sel1:0

tck tdotdi tmstrst_b

dpll1_holdover

dpll1_lock

DPLL2

sck

DPLL1

slave_en

dpll2_ref

rst_b

dpll1_hs_en

cs_b

diff0_en diff1_en

Reference

Monitors

ref

sync

ref

ref0

ref1

ref2

ref3

ref4

ref5

ref6

ref7

sync0

sync1

sync2

int_b

sdh_clk0

sdh_clk1

sdh_fp0

sdh_fp1

p0_clk0

p0_clk1

p0_fp0

p0_fp1

p1_clk0

p1_clk1

fb_clk

ref7:0

sync2:0

ref_&_sync_status

Controller &

State Machine

SPI Interface

SONET/SDH

APLL

Synthesizer

Feedback

Synthesizer

diff0_p/n

diff1_p/n

IEEE 1449.1

JTAG

Master

Clock

fb_clk

ext_fb_fp

ext_fb_clk

osco

osci

fb_fp

sdh_filter filter_ref0 filter_ref1

ZL30116

SONET/SDH

OC-48/OC-192 System Synchronizer

Data Sheet

Ordering Information

ZL30116GGGV2 100 Pin CABGA Trays

ZL30116GGG2V2100 Pin CABGA* Trays

*Pb Free Tin/Silver/Copper

-40

C to +85

ZL30116 Data Sheet

Zarlink Semiconductor Inc.

Applications

• AdvancedTCA

Systems

• Multi-Service Edge Switches or Routers

• Multi-Service Provisioning Platforms (MSPPs)

• Add-Drop Multiplexers (ADMs)

• Wireless/Wireline Gateways

• Wireless Base Stations

• DSLAM / Next Gen DLC

• Core Routers

ZL30116 Data Sheet

Table of Contents

Zarlink Semiconductor Inc.

1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2 DPLL Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.7 Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.8 External Feedback Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

ZL30116GGG2V2

Mfr. #:

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Manufacturer:

Microchip / Microsemi

Description:

Clock Generators & Support Products Rev2 Pb Free Low Jitter System Synch.

Lifecycle:

New from this manufacturer.

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ZL30116GGG2V2

ZL30116GGG2V2

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