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ZL30116GGG2V2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
ZL30116 Data Sheet
25
Zarlink Semiconductor Inc.
31 dpll2_ref_pri_ctrl_0 10 Control register for the ref0 and ref1 priority
values
R/W
32 dpll2_ref_pri_ctrl_1 32 Control register for the ref2 and ref3 priority
values
R/W
33 dpll2_ref_pri_ctrl_2 54 Control register for the ref4 and re5 priority
values
R/W
34 dpll2_ref_pri_ctrl_3 76 Control register for the ref6 and ref7 priority
values
R/W
35 dpll2_lock_holdover_status 04 DPLL2 lock and holdover status register R
P0 Configuration Registers
36 p0_enable 8F Control register to enable p0_clk0, p0_clk1,
p0_fp0, p0_fp1, the P0 synthesizer and select
the source
R/W
37 p0_run 0F Control register to generate p0_clk0, p0_clk1,
p0_fp0 and p0_fp1
R/W
38 p0_freq_0 00 Control register for the [7:0] bits of the N of
N*8k clk0
R/W
39 p0_freq_1 01 Control register for the [13:8] bits of the N of
N*8k clk0
R/W
3A p0_clk0_offset90 00 Control register for the p0_clk0 phase position
coarse tuning
R/W
3B p0_clk1_div 3E Control register for the p0_clk1 frequency
selection
R/W
3C p0_clk1_offset90 00 Control register for the p0_clk1 phase position
coarse tuning
R/W
3D p0_offset_fine 00 Control register for the output/output phase
alignment fine tuning for p0 path
R/W
3E p0_fp0_freq 05 Control register to select the p0_fp0 frame
pulse frequency
R/W
3F p0_fp0_type 83 Control register to select fp0 type R/W
40 p0_fp0_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
R/W
41 p0_fp0_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
R/W
42 p0_fp0_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
43 p0_fp1_freq 05 Control register to select p0_fp1 frame pulse
frequency
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
ZL30116 Data Sheet
26
Zarlink Semiconductor Inc.
44 p0_fp1_type 11 Control register to select fp1 type R/W
45 p0_fp1_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
R/W
46 p0_fp1_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
R/W
47 p0_fp1_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
P1 Configuration Registers
48 p1_enable 83 Control register to enable p1_clk0, p1_clk1, the
P1 synthesizer and select the source
R/W
49 p1_run 03 Control register to generate enable/disable
p1_clk0 and p1_clk1
R/W
4A p1_freq_0 C1 Control register for the [7:0] bits of the N of
N*8k clk0
R/W
4B p1_freq_1 00 Control register for the [13:8] bits of the N of
N*8k clk0
R/W
4C p1_clk0_offset90 00 Control register for the p1_clk0 phase position
coarse tuning
R/W
4D p1_clk1_div 3F Control register for the p1_clk1 frequency
selection
R/W
4E p1_clk1_offset90 00 Control register for the p1_clk1 phase position
coarse tuning
R/W
4F p1_offset_fine 00 Control register for the output/output phase
alignrment fine tuning
R/W
SDH Configuration Registers
50 sdh_enable 8F Control register to enable sdh_clk0, sdh_clk1,
sdh_fp0, sdh_fp1 and the SDH PLL
R/W
51 sdh_run 0F Control register to generate sdh_clk0,
sdh_clk1, sdh_fp0 and sdh_fp1
R/W
52 sdh_clk_div 42 Control register for the sdh_clk0 and sdh_clk1
frequency selection
R/W
53 sdh_clk0_offset90 00 Control register for the sdh_clk0 phase position
coarse tuning
R/W
54 sdh_clk1_offset90 00 Control register for the sdh_clk1 phase position
coarse tuning
R/W
55 sdh_offset_fine 00 Control register for the output/output phase
alignrment fine tuning for sdh path
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
ZL30116 Data Sheet
27
Zarlink Semiconductor Inc.
56 sdh_fp0_freq 05 Control register to select the sdh_fp0 frame
pulse frequency
R/W
57 sdh_fp0_type 23 Control register to select fp0 type R/W
58 sdh_fp0_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
59 sdh_fp0_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5A sdh_fp0_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
5B sdh_fp1_freq 03 Control register to select sdh_fp1 frame pulse
frequency
R/W
5C sdh_fp1_type 03 Control register to select fp1 type R/W
5D sdh_fp1_fine_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5E sdh_fp1_fine_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5F sdh_fp1_coarse_offset 00 Programmable frame pulse phase offset in
multiples of 8 kHz cycles
R/W
Differential Output Configuration
60 diff_ctrl A3 Control register to enable diff0, diff1 R/W
61 diff_sel 53 Control register to select the diff0 and diff1
frequencies
R/W
External Feedback Configuration
62 fb_control 80 Control register to enable fb_clk and the FB
PLL, int/ext feedback select
R/W
63 fb_offset_fine F5 Control register for the output/output phase
alignment fine tuning
R/W
64 reserved
N * 8 kHz Reference Control
65 ref_freq_mode_0 00 Control register to set whether to use auto
detect, CustomA or CustomB for ref0 to ref3
R/W
66 ref_freq_mode_1 00 Control register to set whether to use auto
detect, CustomA or CustomB for ref4 to ref7
R/W
67 custA_mult_0 00 Control register for the [7:0] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

ZL30116GGG2V2

Mfr. #:
Buy ZL30116GGG2V2
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Rev2 Pb Free Low Jitter System Synch.
Lifecycle:
New from this manufacturer.
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