ZL30116 Data Sheet
12
Zarlink Semiconductor Inc.
1.0 Functional Description
The ZL30116 SONET/SDH System Synchronizer is a highly integrated device that provides the functionality
required for synchronizing network equipment. It incorporates two independent DPLLs, each capable of locking to
one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.
1.1 DPLL Features
The ZL30116 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or
frame pulse synchronization. Table 1 shows a feature summary for both DPLLs.
Feature DPLL1 DPLL2
Modes of Operation Free-run, Normal (locked), Holdover Free-run, Normal (locked), Holdover
Loop Bandwidth User selectable: 0.1 Hz, 1.7 Hz, 3.5 Hz,
fast lock (7 Hz), 14 Hz, 28 Hz
1
, or
wideband
2
(890 Hz / 56 Hz / 14 Hz)
Fixed: 14 Hz
Phase Slope Limiting User selectable: 885 ns/s, 7.5 μs/s,
61 μs/s, or unlimited
User selectable: 61 μs/s, or unlimited
Pull-in Range User selectable: 12 ppm, 52 ppm,
83 ppm, 130 ppm
Fixed: 130 ppm
Holdover Parameters Selectable Update Times: 26 ms, 1 s,
10 s, 60 s, and Selectable Holdover
Post Filter BW: 18 mHz, 2.5 Hz, 10 Hz.
Fixed Update Time: 26 ms
No Holdover Post Filtering
Holdover Frequency
Accuracy
Better than 1 ppb (Stratum 3E) initial
frequency offset. Frequency drift
depends on the 20 MHz external
oscillator.
Better than 50 ppb (Stratum 3) initial
frequency offset. Frequency drift
depends on the 20 MHz external
oscillator.
Reference Inputs Ref0 to Ref7 Ref0 to Ref7
Sync Inputs Sync0, Sync1, Sync2 Sync inputs are not supported.
Input Ref Frequencies 2 kHz, N * 8 kHz up to 77.76 MHz 2 kHz, N * 8 kHz up to 77.76 MHz
Supported Sync Input
Frequencies
166.67 Hz, 400 Hz, 1 kHz, 2 kHz,
8kHz, 64kHz.
Sync inputs are not supported.
Input Reference
Selection/Switching
Automatic (based on programmable
priority and revertiveness), or manual
Automatic (based on programmable
priority and revertiveness), or manual
Hitless Ref Switching Can be enabled or disabled Can be enabled or disabled
Output Clocks diff0_p/n, diff1_p/n, sdh_clk0, sdh_clk1,
p0_clk0, p0_clk1, p1_clk0, p1_clk1,
fb_clk.
p0_clk0, p0_clk1, p1_clk0, p1_clk1.
Output Frame Pulses sdh_fp0, sdh_fp1, p0_fp0, p0_fp1
synchronized to active sync reference.
p0_fp0, p0_fp1 not synchronized to sync
reference.
Supported Output Clock
Frequencies
As listed in Table 4 As listed in Table 4 for p0_clk0, p0_clk1,
p1_clk0, p1_clk1
Table 1 - DPLL1 and DPLL2 Features
