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ZL30116GGG2V2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
ZL30116 Data Sheet
22
Zarlink Semiconductor Inc.
2.0 Software Configuration
The ZL30116 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The
device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s
processor, or it can operate in a manual mode where the system processor controls most of the operation of the
device.
The following table provides a summary of the registers available for status updates and configuration of the device.
.
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Miscellaneous Registers
00 id_reg C0 Chip and version identification and reset ready
indication register
R
01 use_hw_ctrl 00 Allows some functions of the device to be
controlled by hardware pins
R/W
Interrupts
02 ref_fail_isr FF Reference failure interrupt service register R
03 dpll1_isr 70 DPLL1 interrupt service register Sticky
R
04 dpll2_isr 00 DPLL2 interrupt service register Sticky
R
05 ref_mon_fail_0 FF Ref0 and ref1 failure indications Sticky
R
06 ref_mon_fail_1 FF Ref2 and ref3 failure indications. Sticky
R
07 ref_mon_fail_2 FF Ref4 and ref5 failure indications Sticky
R
08 ref_mon_fail_3 FF Ref6 and ref7 failure indications Sticky
R
09 ref_fail_isr_mask 00 Reference failure interrupt service register
mask
R/W
0A dpll1_isr_mask 00 DPLL1 interrupt service register mask R/W
0B dpll2_isr_mask 00 DPLL2 interrupt service register mask R/W
0C ref_mon_fail_mask_0 FF Control register to mask each failure indicator
for ref0 and ref1
R/W
0D ref_mon_fail_mask_1 FF Control register to mask each failure indicator
for ref2 and ref3
R/W
0E ref_mon_fail_mask_2 FF Control register to mask each failure indicator
for ref4 and ref5
R/W
Table 5 - Register Map
ZL30116 Data Sheet
23
Zarlink Semiconductor Inc.
0F ref_mon_fail_mask_3 FF Control register to mask each failure indicator
for ref6 and ref7
R/W
Reference Monitor Setup
10 detected_ref_0 FF Ref0 and ref1 auto-detected frequency value
status register
R
11 detected_ref_1 FF Ref2 and ref3 auto-detected frequency value
status register
R
12 detected_ref_2 FF Ref4 and ref5 auto-detected frequency value
status register
R
13 detected_ref_3 FF Ref6 and ref7 auto-detected frequency value
status register
R
14 detected_sync_0 EE Sync0 and sync1 auto-detected frequency
value and sync failure status register
R
15 detected_sync_1 0E Sync2 auto-detected frequency value and sync
valid status register
R
16 oor_ctrl_0 33 Control register for the ref0 and ref1 out of
range limit
R/W
17 oor_ctrl_1 33 Control register for the ref2 and ref3 out of
range limit
R/W
18 oor_ctrl_2 33 Control register for the ref4 and ref5 out of
range limit
R/W
19 oor_ctrl_3 33 Control register for the ref6 and ref7 out of
range limit
R/W
1A gst_mask_0 FF Control register to mask the inputs to the guard
soak timer for ref0 to ref3
R/W
1B gst_mask_1 FF Control register to mask the inputs to the guard
soak timer for ref4 to ref7
R/W
1C gst_qualif_time 1A Control register for the guard_soak_timer
qualification time and disqualification time for
the references
R/W
DPLL1 Control
1D dpll1_ctrl_0 See
Register
Description
Control register for the DPLL1 filter control;
phase slope limit, bandwidth and hitless
switching
R/W
1E dpll1_ctrl_1 See
Register
Description
Holdover update time, filter_out_en,
freq_offset_en, revert enable
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
ZL30116 Data Sheet
24
Zarlink Semiconductor Inc.
1F dpll1_modesel See
Register
Description
Control register for the DPLL1 mode of
operation
R/W
20 dpll1_refsel 00 DPLL1 reference selection or reference
selection status
R/W
21 dpll1_ref_fail_mask 3C Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
R/W
22 dpll1_wait_to_restore 00 Control register to indicate the time to restore a
previous failed reference
R/W
23 dpll1_ref_rev_ctrl 00 Control register for the ref0 to ref7 enable
revertive signals
R/W
24 dpll1_ref_pri_ctrl_0 10 Control register for the ref0 and ref1 priority
values
R/W
25 dpll1_ref_pri_ctrl_1 32 Control register for the ref2 and ref3 priority
values
R/W
26 dpll1_ref_pri_ctrl_2 54 Control register for the ref4 and re5 priority
values
R/W
27 dpll1_ref_pri_ctrl_3 76 Control register for the ref6 and ref7 priority
values
R/W
28 dpll1_lock_holdover_status 04 DPLL1 lock and holdover status register R
29 dpll1_pullinrange 03 Control register for the pull-in range R/W
DPLL2 Control
2A dpll2_ctrl_0 00 Control register to program the DPLL2: hitless
switching, the phase slope limit and DPLL
enable
R/W
2B dpll2_ctrl_1 04 Control register to program the DPLL2:
filter_out_en, freq_offset_en, revert enable
R/W
2C dpll2_modesel 02 Control register to select the mode of operation
of the DPLL2
R/W
2D dpll2_refsel 00 DPLL2 reference selection or reference
selection status
R/W
2E dpll2_ref_fail_mask 3C Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
R/W
2F dpll2_wait_to_restore 00 Control register to indicate the time to restore a
previous failed reference for the DPLL2 path
R/W
30 dpll2_ref_rev_ctrl 00 Control register for the ref0 to ref7 enable
revertive signals
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

ZL30116GGG2V2

Mfr. #:
Buy ZL30116GGG2V2
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Rev2 Pb Free Low Jitter System Synch.
Lifecycle:
New from this manufacturer.
Delivery:
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