ZL30116 Data Sheet
16
Zarlink Semiconductor Inc.
1.4 Ref and Sync Monitoring
All input references (ref0 to ref7) are monitored for frequency accuracy and phase regularity. New references are
qualified before they can be selected as a synchronization source and qualified references are continuously
monitored to ensure that they are suitable for synchronization. The process of qualifying a reference depends on
four levels of monitoring.
Single Cycle Monitor (SCM)
The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock
edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure
(scm_fail) is declared.
Coarse Frequency Monitor (CFM)
The CFM block monitors the reference frequency over a measurement period of 30 μs so that it can quickly detect
large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by more than 3%
or approximately 30000 ppm.
Precise Frequency Monitor (PFM)
The PFM block measures the frequency accuracy of the reference over a 10 second interval. To ensure an
accurate frequency measurement, the PFM measurement interval is re-initiated if phase or frequency irregularities
are detected by the SCM or CFM. The PFM provides a level of hysteresis between the acceptance range and the
rejection range to prevent a failure indication from toggling between valid and invalid for references that are on the
edge of the acceptance range.
When determining the frequency accuracy of the reference input, the PFM uses the external oscillator’s output
frequency (f
ocsi
) as its point of reference.
Guard Soak Timer (GST)
The GST block mimics the operation of an analog integrator by accumulating failure events from the CFM and the
SCM blocks and applying a selectable rate of decay when no failures are detected.
As shown in Figure 5, a GST failure (gst_fail) is triggered when the accumulated failures have reached the upper
threshold during the disqualification observation window. When there are no CFM or SCM failures, the accumulator
decrements until it reaches its lower threshold during the qualification window.
Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures
ref
CFM or SCM failures
upper threshold
lower threshold
t
d
- disqualification time
t
q
- qualification time = n * t
d
t
d
t
q
gst_fail
ZL30116 Data Sheet
17
Zarlink Semiconductor Inc.
All sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference
clock cycles within the frame pulse period.
1.5 Output Clocks and Frame Pulses
The ZL30116 offers a wide variety of outputs including two low-jitter differential LVPECL clocks (diff0_p/n,
diff1_p/n), two SONET/SDH LVCMOS (sdh_clk0, sdh_clk1) output clocks, and four programmable LVCMOS
(p0_clk0, p0_clk1, p1_clk0, p1_clk1) output clocks. In addition to the clock outputs, two LVCMOS SONET/SDH
frame pulse outputs (sdh_fp0, sdh_fp1) and two LVCMOS programmable frame pulses (p0_fp0, p0_fp1) are also
available.
The feedback clock (fb_clk) of DPLL1 is available as an output clock. Its output frequency is always equal to
DPLL1’s selected input frequency.
The output clocks and frame pulses derived from the SONET/SDH APLL are always synchronous with DPLL1, and
the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1
or DPLL2. This allows the ZL30116 to have two independent timing paths.
Figure 6 - Output Clock Configuration
DPLL2
p0_clk0
p0_fp0
p0_clk1
p0_fp1
P0
Synthesizer
DPLL1
p1_clk0
p1_clk1
P1
Synthesizer
sdh_clk0
sdh_fp0
sdh_clk1
sdh_fp1
SONET/SDH
APLL
diff0
diff1
Feedback
Synthesizer
fb_clk
ZL30116 Data Sheet
18
Zarlink Semiconductor Inc.
The supported frequencies for the output clocks and frame pulses are shown in Table 4.
diff0_p/n,
diff1_p/n
(LVPECL)
sdh_clk0,
sdh_clk1
(LVCMOS)
p0_clk0, p1_clk0
(LVCMOS)
p0_clk1, p1_clk1
(LVCMOS)
sdh_fp0, shd_fp1,
p0_fp0, p0_fp1
(LVCMOS)
6.48 MHz 6.48 MHz 2 kHz p
x
_clk0
p
x
_clk1 =
2
M
(Up to 77.76 MHz)
1
1. M= -128 to 127 defined as an 8-bit two’s complement value. +ve values divide, -ve values multiply
166.67 Hz
(48x 125 μs frames)
19.44 MHz 9.72 MHz N * 8 kHz
(up to 77.76 MHz)
2
2. N = 0 to 9270, N = 0 selects 2 kH
400 Hz
38.88 MHz 12.96 MHz 1 kHz
51.84 MHz 19.44 MHz 2 kHz
77.76 MHz 25.92 MHz 4 kHz
155.52 MHz 38.88 MHz 8 kHz
311.04 MHz 51.84 MHz 32 kHz
622.08 MHz 77.76 MHz 64 kHz
Table 4 - Output Clock and Frame Pulse Frequencies

ZL30116GGG2V2

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Rev2 Pb Free Low Jitter System Synch.
Lifecycle:
New from this manufacturer.
Delivery:
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