ZL30116GGG2V2 Datasheet ZL30116GGG2V2, ZL30116GGGV2 | P13-P15

ZL30116 Data Sheet

Zarlink Semiconductor Inc.

1.2 DPLL Mode Control

Both DPLL1 and DPLL2 independently support three modes of operation - free-run, normal, and holdover. The

mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2.

Figure 2 - Automatic Mode State Machine

Free-run

The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a

reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the

external master oscillator.

Lock Acquisition

The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the

input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given

a stable reference input, the ZL30116 will enter in the Normal (locked) mode.

Supported Output

Frame Pulse

Frequencies

As listed in Table 4 As listed in Table 4 for p0_fp0, p0_fp not

synchronized to sync reference.

External Status Pin

Indicators

Lock, Holdover None

1. Limited to 14 Hz for 2 kHz references)

2. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies greater than

8 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to 8 kHz, the loop bandwidth = 56 Hz. The loop bandwidth is

equal to 14 Hz for reference frequencies of 2 kHz.

Feature DPLL1 DPLL2

Table 1 - DPLL1 and DPLL2 Features

Reset

Another reference is

qualified and available

for selection

Phase lock on

the selected

reference is

achieved

Lock

Acquisition

Normal

(Locked)

No references are

qualified and available

for selection

Free-Run

Holdover

Selected reference

fails

All references are monitored for

frequency accuracy and phase

regularity, and at least one

reference is qualified.

Normal

(Locked)

ZL30116 Data Sheet

Zarlink Semiconductor Inc.

Normal (locked)

The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified

reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency

accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with

the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication

standards.

Holdover

When the DPLL operating in the normal mode loses its reference input, and no other qualified references are

available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data

collected while the DPLL was synchronized. The transition between normal and holdover modes is controlled by

the DPLL so that its initial frequency offset is better than 1 ppb which meets the requirement of Stratum 3E. The

frequency drift after this transition period is dependant on the frequency drift of the external master oscillator.

1.3 Ref and Sync Inputs

There are eight reference clock inputs (ref0 to ref7) available to both DPLL1 and DPLL2. The selected reference

input is used to synchronize the output clocks. Each of the DPLLs have independent reference selectors which can

be controlled using a built-in state machine or set in a manual mode.

Figure 3 - Reference and Sync Inputs

Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz.

Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is

within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz

are also available.

2 kHz 16.384 MHz

8 kHz 19.44 MHz

64 kHz 38.88 MHz

1.544 MHz 77.76 MHz

2.048 MHz

6.48 MHz

8.192 MHz

Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies

ref7:0

sync2:0

DPLL2

DPLL1

ZL30116 Data Sheet

Zarlink Semiconductor Inc.

In addition to the reference inputs, DPLL1 has three optional frame pulse synchronization inputs (sync0 to sync2)

used to align the output frame pulses. The sync

input is selected with its corresponding ref

input, where n = 0, 1,

or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of the

frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.

Figure 4 - Output Frame Pulse Alignment

Each of the sync inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising

edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width

requirement of 5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies

shown in Table 3.

166.67 Hz

(48x 125 μs frames)

400 Hz

1 kHz

2 kHz

8 kHz

64 kHz

Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies

ref

diff

/sdh_clk

/p0_clk

/p1_clk

sdh_fp

/p0_fp

Without a frame pulse

signal at the sync

input, the output

frame pulses will align

to any arbitrary cycle

of its associated

output clock.

sync

- no frame pulse signal present

When a frame pulse

signal is present at

the sync input, the

DPLL will align the

output frame pulses

to the output clock

edge that is aligned

to the input frame

pulse.

ref

sync

n = 0, 1, 2

x = 0, 1

n = 0, 1, 2

x = 0, 1

diff

/sdh_clk

/p0_clk

/p1_clk

sdh_fp

/p0_fp

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ZL30116GGG2V2

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