ZL30116 Data Sheet
19
Zarlink Semiconductor Inc.
1.6 Configurable Input-to-Output and Output-to-Output Delays
The ZL30116 allows programmable static delay compensation for controlling input-to-output and output-to-output
delays of its clocks and frame pulses.
All of the output synthesizers (SONET/SDH, P0, P1, Feedback) locked to DPLL1 can be configured to lead or lag
the selected input reference clock using the DPLL1 Fine Delay. The delay is programmed in steps of 119.2 ps with
a range of -128 to +127 steps giving a total delay adjustment in the range of -15.26 ns to +15.14 ns. Negative
values delay the output clock, positive values advance the output clock. Synthesizers that are locked to DPLL2 are
unaffected by this delay adjustment.
In addition to the fine delay introduced in the DPLL1 path, the SONET/SDH, P0, and P1 synthesizers have the
ability to add their own fine delay adjustments using the P0 Fine Delay, P1 Fine Delay, and SDH Fine Delay.
These delays are also programmable in steps of 119.2 ps with a range of -128 to +127 steps.
In addition to these delays, the single-ended output clocks of the SONET/SDH, P0, and P1 synthesizers can be
independently offset by 90, 180 and 270 degrees using the Coarse Delay, and the SONET/SDH differential outputs
can be independently delayed by -1.6 ns, 0 ns, +1.6 ns or +3.2 ns using the Diff Delay. The output frame pulses
(SONET/SDH, P0) can be independently offset with respect to each other using the FP Delay.
Figure 7 - Phase Delay Adjustments
DPLL1
DPLL2
P0 Fine Delay
p0_clk0
p0_clk1
p0_fp0
p0_fp1
P0
Synthesizer
Coarse Delay
Coarse Delay
FP Delay
FP Delay
fb_clk
p1_clk0
p1_clk1
P1 Fine Delay
Diff Delay
Diff Delay
diff0
diff1
SONET/SDH
APLL
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
SDH Fine Delay
Feedback
Synthesizer
DPLL1 Fine Delay
Coarse Delay
Coarse Delay
FP Delay
FP Delay
Coarse Delay
Coarse Delay
P1
Synthesizer
