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ZL30116GGG2V2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
ZL30116 Data Sheet
7
Zarlink Semiconductor Inc.
Pin Description
Pin # Name
I/O
Type
Description
Input Reference
C1
B2
A3
C3
B3
B4
C4
A4
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
I
d
Input References (LVCMOS, Schmitt Trigger). These are input references
available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight
input references can be automatically or manually selected using software
registers. These pins are internally pulled down to Vss.
B1
A1
A2
sync0
sync1
sync2
I
d
Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger).
These are the frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled down to V
ss.
C5 ext_fb_clk I
d
External DPLL Feedback Clock (LVCMOS, Schmitt Trigger). External
feedback clock input. This allows DPLL1 to adjust for PCB trace propagation
delays. This pin is internally pulled down to Vss. Leave open when not is use.
B5 ext_fb_fp I
d
External DPLL Feedback Frame Pulse (LVCMOS, Schmitt Trigger). External
feedback frame pulse input. This allows DPLL1 to adjust for PCB trace
propagation delays. This pin is internally pulled down to Vss. Leave open when
not is use.
Output Clocks and Frame Pulses
D10 sdh_clk0 O SONET/SDH Output Clock 0 (LVCMOS). This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 77.76 MHz.
G10 sdh_clk1 O SONET/SDH Output Clock 1 (LVCMOS). This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 19.44 MHz.
E10 sdh_fp0 O SONET/SDH Output Frame Pulse 0 (LVCMOS). This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 8 kHz.
F10 sdh_fp1 O SONET/SDH Output Frame Pulse 1 (LVCMOS). This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 2 kHz.
K9 p0_clk0 O Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 2.048 MHz.
K7 p0_clk1 O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p0_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 8.192 MHz.
ZL30116 Data Sheet
8
Zarlink Semiconductor Inc.
K8 p0_fp0 O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
J7 p0_fp1 O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz
J10 p1_clk0 O Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1).
K10 p1_clk1 O Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p1_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 3.088 MHz (2x DS1).
H10 fb_clk O Feedback Clock (LVCMOS). This output is a buffered copy of the feedback
clock for DPLL1. The frequency of this output always equals the frequency of the
selected reference.
E1 dpll2_ref O DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the
output of the reference selector for DPLL2. Switching between input reference
clocks at this output is not hitless.
A9
B10
diff0_p
diff0_n
O Differential Output Clock 0 (LVPECL). This output can be configured to provide
any one of the available SDH clocks. The default frequency for this clock output
is 155.52 MHz
A10
B9
diff1_p
diff1_n
O Differential Output Clock 1 (LVPECL). This output can be configured to provide
any one of the available SDH clocks. The default frequency for this clock output
is 622.08 MHz clock
Control
H5 rst_b I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To
ensure proper operation, the device must be reset after power-up. Reset should
be asserted for a minimum of 300 ns.
J5 dpll1_hs_en I
u
DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at
this input enables hitless reference switching. A logic low disables hitless
reference switching and re-aligns DPLL1’s output phase to the phase of the
selected reference input. This feature can also be controlled through software
registers. This pin is internally pulled up to Vdd.
C2
D2
dpll1_mod_sel0
dpll1_mod_sel1
I
u
DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels
on these pins determine the default mode of operation for DPLL1 (Automatic,
Normal, Holdover or Freerun). After reset, the mode of operation can be
controlled directly with these pins, or by accessing the dpll1_modesel register
(0x1F) through the serial interface. This pin is internally pulled up to Vdd.
D1 slave_en I
u
Master/Slave control (LVCMOS, Schmitt Trigger). This pin selects the mode of
operation for the device. If set high, slave mode is selected. If set low, master
mode is selected. This feature can also be controlled through software registers.
This pin is internally pulled up to Vdd.
Pin # Name
I/O
Type
Description
ZL30116 Data Sheet
9
Zarlink Semiconductor Inc.
K1 diff0_en I
u
Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output 0 driver is enabled. When set low, the differential
driver is tristated reducing power consumption. This pin is internally pulled up to
Vdd.
D3 diff1_en I
u
Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output 1 driver is enabled. When set low, the differential
driver is tristated reducing power consumption.This pin is internally pulled up to
Vdd.
Status
H1 dpll1_lock O Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output
goes high when DPLL1’s output is frequency and phase locked to the input
reference.
J1 dpll1_holdover O Holdover Indicator (LVCMOS). This pin goes high when DPLL1 enters the
holdover mode.
Serial Interface
E2 sck I Clock for Serial Interface (LVCMOS). Serial interface clock.
F1 si I Serial Interface Input (LVCMOS). Serial interface data input pin.
G1 so O Serial Interface Output (LVCMOS). Serial interface data output pin.
E3 cs_b I
u
Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This
pin is internally pulled up to Vdd.
G2 int_b O Interrupt Pin (LVCMOS). Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pulled up to VDD.
APLL Loop Filter
A6 sdh_filter A External Analog PLL Loop Filter terminal.
B6 filter_ref0 A Analog PLL External Loop Filter Reference.
C6 filter_ref1 A Analog PLL External Loop Filter Reference.
JTAG and Test
J4 tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on the
falling edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
K2 tdi I
u
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it
should be left unconnected.
H4 trst_b I
u
Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-
up to ensure that the device is in the normal functional state. This pin is internally
pulled up to Vdd. If this pin is not used then it should be connected to GND.
K3 tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not
used then it should be pulled down to GND.
Pin # Name
I/O
Type
Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

ZL30116GGG2V2

Mfr. #:
Buy ZL30116GGG2V2
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Rev2 Pb Free Low Jitter System Synch.
Lifecycle:
New from this manufacturer.
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