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ZL30116GGG2V2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
ZL30116 Data Sheet
List of Figures
4
Zarlink Semiconductor Inc.
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Automatic Mode State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6 - Output Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8 - Typical Master/Slave Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9 - External Feedback Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ZL30116 Data Sheet
List of Tables
5
Zarlink Semiconductor Inc.
Table 1 - DPLL1 and DPLL2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5 - Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ZL30116 Data Sheet
6
Zarlink Semiconductor Inc.
Changes Summary
The following table captures the changes from the June 2006 issue.
The following table captures the changes from the January 2006 issue.
The following table captures the changes from the December 2005 issue.
Page Item Change
2 Ordering Information box Updated new ordering part numbers.
22 Table 5 - Register Map Correct chip id_reg number.
Page Item Change
25-27 Software Register Description Changed the naming and description of the frame
pulse delay offset registers to clearly show that
they form a 22-bit register spread out over 3 8-bit
registers. The 22-bit register must be considered a
multi-byte register during a read or write operation.
This affects registers 0x40-0x42, 0x45-0x47, and
0x58-0x5A.
Page Item Change
12 1.1, “DPLL Features“ Added 14 Hz and 28 Hz to available loop
bandwidths for DPLL1
14 Table 2 Removed the Custom frequencies from the auto-
detect table. Custom frequencies are
configurable for each reference.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

ZL30116GGG2V2

Mfr. #:
Buy ZL30116GGG2V2
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Rev2 Pb Free Low Jitter System Synch.
Lifecycle:
New from this manufacturer.
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