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5962-9957201NNA

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
QPro Virtex 2.5V QML High-Reliability FPGAs
10
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
R
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Symbol Description
Speed Grade
Units
-4
Min Max
Combinatorial Delays
T
ILO
4-input function: F/G inputs to X/Y outputs - 0.8 ns
T
IF5
5-input function: F/G inputs to F5 output - 0.9 ns
T
IF5X
5-input function: F/G inputs to X output - 1.0 ns
T
IF6Y
6-input function: F/G inputs to Y output via F6 MUX - 1.2 ns
T
F5INY
6-input function: F5IN input to Y output - 0.5 ns
T
IFNCTL
Incremental delay routing through transparent latch to XQ/YQ outputs - 0.8 ns
T
BYYB
BY input to YB output - 0.7 ns
Sequential Delays
T
CKO
FF clock CLK to XQ/YQ outputs - 1.4 ns
T
CKLO
Latch clock CLK to XQ/YQ outputs - 1.6 ns
Setup and Hold Times before/after Clock CLK Setup Time / Hold Time
T
ICK
/T
CKI
4-input function: F/G Inputs 1.5 / 0 - ns
T
IF5CK
/T
CKIF5
5-input function: F/G inputs 1.7 / 0 - ns
T
F5INCK
/T
CKF5IN
6-input function: F5IN input 1.2 / 0 - ns
T
IF6CK
/T
CKIF6
6-input function: F/G inputs via F6 MUX 1.9 / 0 - ns
T
DICK
/T
CKDI
BX/BY inputs 0.8 / 0 - ns
T
CECK
/T
CKCE
CE input 1.0 / 0 - ns
T
RCK
T
CKR
SR/BY inputs (synchronous) 0.9 / 0 - ns
Clock CLK
T
CH
Minimum pulse width, High 2.0 - ns
T
CL
Minimum pulse width, Low 2.0 - ns
Set/Reset
T
RPW
Minimum pulse width, SR/BY inputs 3.3 - ns
T
RQ
Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) - 1.4 ns
T
IOGSRQ
Delay from GSR to XQ/YQ outputs - 12.5 ns
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
www.xilinx.com
11
Preliminary Product Specification
1-800-255-7778
R
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Symbol Description
Speed Grade
Units
-4
Min Max
Combinatorial Delays
T
OPX
F operand inputs to X via XOR - 1.0 ns
T
OPXB
F operand input to XB output - 1.4 ns
T
OPY
F operand input to Y via XOR - 2.0 ns
T
OPYB
F operand input to YB output - 2.0 ns
T
OPCYF
F operand input to COUT output - 1.5 ns
T
OPGY
G operand inputs to Y via XOR - 1.2 ns
T
OPGYB
G operand input to YB output - 2.1 ns
T
OPCYG
G operand input to COUT output - 1.6 ns
T
BXCY
BX initialization input to COUT - 1.1 ns
T
CINX
CIN input to X output via XOR - 0.6 ns
T
CINXB
CIN input to XB - 0.1 ns
T
CINY
CIN input to Y via XOR - 0.6 ns
T
CINYB
CIN input to YB - 0.6 ns
T
BYP
CIN input to COUT output - 0.2 ns
Multiplier Operation
T
FANDXB
F1/2 operand inputs to XB output via AND - 0.5 ns
T
FANDYB
F1/2 operand inputs to YB output via AND - 1.1 ns
T
FANDCY
F1/2 operand inputs to COUT output via AND - 0.6 ns
T
GANDYB
G1/2 operand inputs to YB output via AND - 0.7 ns
T
GANDCY
G1/2 operand inputs to COUT output via AND - 0.2 ns
Setup and Hold Times before/after Clock CLK Setup Time / Hold Time
T
CCKX
/T
CKCX
CIN input to FFX 1.3 / 0 - ns
T
CCKY
/T
CKCY
CIN input to FFY 1.4 / 0 - ns
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if
a “0” is listed, there is no positive hold time.
QPro Virtex 2.5V QML High-Reliability FPGAs
12
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
R
CLB SelectRAM Switching Characteristics
BLOCKRAM Switching Characteristics
Symbol Description
Speed Grade
Units
-4
Min Max
Sequential Delays
T
SHCKO
Clock CLK to X/Y outputs (WE active) - 3.0 ns
Shift-Register Mode
T
SHCKO
Clock CLK to X/Y outputs - 3.0 ns
Setup Times before Clock CLK Setup Time / Hold Time
T
AS
/T
AH
F/G address inputs 0.7 / 0 - ns
T
DS
/T
DH
BX/BY data inputs (DIN) 0.9 / 0 - ns
T
WS
/T
WH
CE input (WE) 1.0 / 0 - ns
Shift-Register Mode
T
SHDICK
BX/BY data inputs (DIN) 0.9 - ns
T
SHCECK
CE input (WS) 1.0 - ns
Clock CLK
T
WPH
Minimum pulse width, High 3.1 - ns
T
WPL
Minimum pulse width, Low 3.1 - ns
T
WC
Minimum clock period to meet address write cycle time 6.2 - ns
Shift-Register Mode
T
SRPH
Minimum pulse width, High 3.1 - ns
T
SRPL
Minimum pulse width, Low 3.1 - ns
Symbol Description
Speed Grade
Units
-4
Min Max
Sequential Delays
T
BCKO
Clock CLK to DOUT output - 4.1 ns
Setup Times Before Clock Clk
T
BACK
/T
BCKA
ADDR inputs 1.5 / 0 - ns
T
BDCK
/T
BCKD
DIN inputs 1.5 / 0 - ns
T
BECK
/T
BCKE
EN input 3.4 / 0 - ns
T
BRCK
/T
BCKR
RST input 3.2 / 0 - ns
T
BWCK
/T
BCKW
WEN input 3.0 / 0 - ns
Clock CLK
T
BPWH
Minimum pulse width, High 2.0 - ns
T
BPWL
Minimum pulse width, Low 2.0 - ns
T
BCCS
CLKA -> CLKB setup time for different ports 4.0 - ns
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

5962-9957201NNA

Mfr. #:
Buy 5962-9957201NNA
Manufacturer:
Xilinx
Description:
IC FPGA 2.5V HIREL VIRTEX 300
Lifecycle:
New from this manufacturer.
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