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5962-9957201NNA

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
QPro Virtex 2.5V QML High-Reliability FPGAs
4
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
R
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages.
Values for I
OL
and I
OH
are guaranteed output currents over
the recommended operating conditions at the V
OL
and V
OH
test points. Only selected standards are tested. These are
chosen to ensure that all standards meet their specifica-
tions. The selected standards are tested at minimum V
CCO
with the respective V
OL
and V
OH
voltage levels shown.
Other standards are sample tested.
Input/Output
Standard
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
V, min V, max V, min V, max V, max V, min mA mA
LVTTL
(1)
–0.5 0.8 2.0 5.5 0.4 2.4 24 –24
LVCM OS 2 –0.5 0.7 1.7 5.5 0.4 1.9 12 –12
PCI, 3.3V –0.5 44% V
CCINT
60% V
CCINT
V
CCO
+ 0.5 10% V
CCO
90% V
CCO
(2) (2)
PCI, 5.0V –0.5 0.8 2.0 5.5 0.55 2.4
(2) (2)
GTL –0.5 V
REF
– 0.05 V
REF
+ 0.05 3.6 0.4 n/a 40 n/a
GTL+ –0.5 V
REF
– 0.1 V
REF
+ 0.1 3.6 0.6 n/a 36 n/a
HSTL I –0.5 V
REF
– 0.1 V
REF
+ 0.1 3.6 0.4 V
CCO
– 0.4 8 -8
HSTL III –0.5 V
REF
– 0.1 V
REF
+ 0.1 3.6 0.4 V
CCO
– 0.4 24 –8
HSTL IV –0.5 V
REF
– 0.1 V
REF
+ 0.1 3.6 0.4 V
CCO
– 0.4 48 –8
SSTL3 I –0.5 V
REF
– 0.2 V
REF
+ 0.2 3.6 V
REF
– 0.6 V
REF
+ 0.6 8 –8
SSTL3 II –0.5 V
REF
– 0.2 V
REF
+ 0.2 3.6 V
REF
– 0.8 V
REF
+ 0.8 16 –16
SSTL2 I –0.5 V
REF
– 0.2 V
REF
+ 0.2 3.6 V
REF
– 0.65 V
REF
+ 0.65 7.6 –7.6
SSTL2 II –0.5 V
REF
– 0.2 V
REF
+ 0.2 3.6 V
REF
– 0.80 V
REF
+ 0.80 15.2 –15.2
CTT –0.5 V
REF
– 0.2 V
REF
+ 0.2 3.6 V
REF
– 0.4 V
REF
+ 0.4 8 –8
AGP –0.5 V
REF
– 0.2 V
REF
+ 0.2 3.6 10% V
CCO
90% V
CCO
(2) (2)
Notes:
1. V
OL
and V
OH
for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
www.xilinx.com
5
Preliminary Product Specification
1-800-255-7778
R
Virtex Switching Characteristics
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Virtex devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for
LVTTL levels. For other standards, adjust the delays with
the values shown in "IOB Input Switching Characteristics
Standard Adjustments" on page 6.
Symbol Description Device
Speed Grade
Units
-4
Min Max
Propagation Delays
T
IOPI
Pad to I output, no delay All - 1.0 ns
T
IOPID
Pad to I output, with delay XQV100 - 1.9 ns
XQV300 - 1.9 ns
XQV600 - 2.3 ns
XQV1000 - 2.7 ns
T
IOPLI
Pad to output IQ via transparent latch, no
delay
All - 2.0 ns
T
IOPLID
Pad to output IQ via transparent latch, with
delay
XQV100 - 4.8 ns
XQV300 - 5.1 ns
XQV600 - 5.5 ns
XQV1000 - 5.9 ns
Sequential Delays
T
IOCKIQ
Clock CLK to output IQ All - 0.8 ns
Setup and Hold Times with Respect to Clock CLK Setup Time / Hold Time
T
IOPICK
/ T
IOICKP
Pad, no delay All 2.0 / 0 - ns
T
IOPICKD
/ T
IOICKPD
Pad, with delay All 5.0 / 0 - ns
T
IOICECK
/ T
IOCKICE
ICE input All 1.0 / 0 - ns
T
IOSRCKI
/ T
IOCKISR
SR input (IFF, synchronous) All 1.3 / 0 - ns
Set/Reset Delays
T
IOSRIQ
SR input to IQ (asynchronous) All - 1.8 ns
T
GSRQ
GSR to output IQ All - 12.5 ns
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”,
but if a “0” is listed, there is no positive hold time.
QPro Virtex 2.5V QML High-Reliability FPGAs
6
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
R
IOB Input Switching Characteristics Standard Adjustments
Symbol Description Standard
Speed Grade
Units-4
Data Input Delay Adjustments
T
ILVTTL
Standard-specific data input delay adjustments LVTTL 0.0 ns
T
ILVCMOS2
LV C M OS 2 –0.05 ns
T
IPCI33_3
PCI, 33 MHz, 3.3V –0.14 ns
T
IPCI33_5
PCI, 33 MHz, 5.0V 0.33 ns
T
IGTL
GTL 0.26 ns
T
IGTLP
GTL+ 0.14 ns
T
IHSTL
HSTL 0.04 ns
T
ISSTL2
SSTL2 –0.10 ns
T
ISSTL3
SSTL3 –0.06 ns
T
ICTT
CTT 0.02 ns
T
IAGP
AGP –0.08 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

5962-9957201NNA

Mfr. #:
Buy 5962-9957201NNA
Manufacturer:
Xilinx
Description:
IC FPGA 2.5V HIREL VIRTEX 300
Lifecycle:
New from this manufacturer.
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