QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
www.xilinx.com
25
Preliminary Product Specification
1-800-255-7778
R
IO_VREF_5 79
IO 80
IO 81
IO 82
VCCINT 83
GCK1 84
VCCO 85
GND 86
GCKO 87
IO 88
IO 89
IO 90
IO 91
IO_VREF_4 92
IO 93
IO 94
VCCO 95
IO 96
IO 97
IO 98
VCCINT 99
GND 100
IO 101
IO_VREF_4 102
IO 103
IO 104
IO_VREF_4 105
GND 106
IO 107
IO 108
IO_VREF_4 109
IO 110
IO 111
IO 112
GND 113
DONE 114
VCCO 115
PROGRAM 116
IO_INIT 117
IO_D7 118
Table 5:
CQFP Package (CB228) (Continued)
Function Pin No.
IO 119
IO_VREF_3 120
IO 121
IO 122
GND 123
IO_VREF_3 124
IO 125
IO 126
IO_VREF_3 127
IO_D6 128
GND 129
VCCINT 130
IO_D5 131
IO 132
VCCO 133
IO 134
IO 135
IO_VREF_3 136
IO_D4 137
IO 138
IO 139
VCCINT 140
IO_TRDY 141
VCCO 142
GND 143
IO_IRDY 144
IO 145
IO 146
IO 147
IO_D3 148
IO_VREF_2 149
IO 150
IO 151
VCCO 152
IO 153
IO 154
IO_D2 155
VCCINT 156
GND 157
IO_D1 158
Table 5:
CQFP Package (CB228) (Continued)
Function Pin No.
QPro Virtex 2.5V QML High-Reliability FPGAs
26
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
R
IO_VREF_2 159
IO 160
IO 161
IO_VREF_2 162
GND 163
IO 164
IO 165
IO_VREF_2 166
IO 167
IO_DIN_D0 168
IO_DOUT_BUSY 169
CCLK 170
VCCO 171
TDO 172
GND 173
TDI 174
IO_CS 175
IO_WRITE 176
IO 177
IO_VREF_1 178
IO 179
GND 180
IO_VREF_1 181
IO 182
IO 183
IO_VREF_1 184
IO 185
GND 186
VCCINT 187
IO 188
IO 189
IO 190
VCCO 191
IO 192
IO 193
IO_VREF_1 194
IO 195
IO 196
IO 197
IO 198
Table 5:
CQFP Package (CB228) (Continued)
Function Pin No.
GCK2 199
GND 200
VCCO 201
GCK3 202
VCCINT 203
IO 204
IO 205
IO 206
IO_VREF_0 207
IO 208
IO 209
VCCO 210
IO 211
IO 212
IO 213
VCCINT 214
GND 215
IO 216
IO_VREF_0 217
IO 218
IO 219
IO_VREF_0 220
GND 221
IO 222
IO 223
IO_VREF_0 224
IO 225
IO 226
TCK 227
VCCO 228
GND 1, 8, 14, 27, 42, 48,
56, 66, 72, 86, 100,
106, 113, 123, 129,
143, 157, 163, 173,
180, 186, 200, 215,
221
VCCINT 15, 30, 41, 73, 83, 99,
130, 140, 156, 187,
203, 214
VCCO 18, 28, 37, 58, 76, 85,
95, 115, 133, 142,
152, 171, 191, 201,
210, 228
Table 5:
CQFP Package (CB228) (Continued)
Function Pin No.
QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
www.xilinx.com
27
Preliminary Product Specification
1-800-255-7778
R
Pinout Diagrams
The following diagrams illustrate the locations of spe-
cial-purpose pins on Virtex FPGAs. Ta bl e 6 lists the sym-
bols used in these diagrams. The diagrams also show
I/O-bank boundaries.
Table 6:
Pinout Diagram Symbols
Symbol
Pin Function
S General I/O
d Device-dependent general I/O, n/c on
smaller devices
VV
CCINT
v Device-dependent V
CCINT
, n/c on smaller
devices
OV
CCO
RV
REF
r Device-dependent V
REF
, remains I/O on
smaller devices
G Ground
Ø, 1, 2, 3 Global Clocks
,
,
M0, M1, M2
,
,
,
,
,
,
,
D0/DIN, D1, D2, D3, D4, D5, D6, D7
BDOUT/BUSY
DDONE
PPROGRAM
IINIT
K CCLK
WWRITE
SCS
T Boundary-scan test aAccess port
+ Temperature diode, anode
Temperature diode, cathode
n No connect
Table 6:
Pinout Diagram Symbols
Symbol
Pin Function

5962-9957201NNA

Mfr. #:
Manufacturer:
Xilinx
Description:
IC FPGA 2.5V HIREL VIRTEX 300
Lifecycle:
New from this manufacturer.
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