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5962-9957201NNA

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
QPro Virtex 2.5V QML High-Reliability FPGAs
16
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
R
DLL Timing Parameters
Switching parameters testing is modeled after testing meth-
ods specified by MIL-M-38510/605; all devices are 100 per-
cent functionally tested. Because of the difficulty in directly
measuring many internal timing parameters, those parame-
ters are derived from benchmark timing patterns. The fol-
lowing guidelines reflect worst-case values across the
recommended operating conditions.
Symbol Description
Speed Grade -4
UnitsMin Max
F
CLKINHF
Input clock frequency (CLKDLLHF) 60 180 MHz
F
CLKINLF
Inputclock frequency (CLKDLL) 25 90 MHz
T
DLLPWHF
Input clock pulse width (CLKDLLHF) 2.4 - ns
T
DLLPWLF
Input clock pulse width (CLKDLL) 3.0 - ns
Notes:
1. All specifications correspond to Commercial Operating Temperatures (0°C to +100°C).
Symbol Description
CLKDLLHF CLKDLL
UnitsMin Max Min Max
T
IPTOL
Input clock period tolerance - 1.0 - 1.0 ns
T
IJITCC
Input clock jitter cycle to cycle -
±
150 -
±
300 ps
T
LOCK
Time required for DLL to acquire Lock
F
CLKIN
> 60 MHz - 20 - 20
µ
s
50-60 MHz - - - 25
µ
s
40-50 MHz - - - 50
µ
s
30-40 MHz - - - 90
µ
s
25-30 MHz - - - 120
µ
s
T
SKEW
DLL output skew (between any DLL output) -
±
150 -
±
150 ps
T
OPHASE
DLL output long term phase differential -
±
100 -
±
100 ps
T
OJITCC
DLL output ditter cycle to cycle -
±
60 -
±
60 ps
Notes:
1. All specifications correspond to Commercial Operating Temperatures (0°C to +100°C).
Figure 1:
Frequency Tolerance and Clock Jitter
T
CLKIN
T
CLKIN
+ T
IPTOL
Period Tolerance:
the allowed input clock period change in nanoseconds.
Clock Jitter:
the difference between an ideal reference clock edgfe and the actual design.
T
OJITCC
+
_
_
DS002_01_060100
QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
www.xilinx.com
17
Preliminary Product Specification
1-800-255-7778
R
QPro Virtex Pinouts
Pinout Tables
See the Xilinx WebLINX web site (http://www.xil-
inx.com/partinfo/databook.htm) for updates or additional
pinout information. For convenience, Ta bl e 3 , Ta b l e 4 and
Ta b l e 5 list the locations of special-purpose and power-sup-
ply pins. Pins not listed are user I/Os.
Table 3:
Virtex QFP Package Pinout Information
Pin Name Device PQ/HQ240
GCK0 All 92
GCK1 All 89
GCK2 All 210
GCK3 All 213
M0 All 60
M1 All 58
M2 All 62
CCLK All 179
PROGRAM All 122
DONE All 120
INIT All 123
BUSY/DOUT All 178
D0/DIN All 177
D1 All 167
D2 All 163
D3 All 156
D4 All 145
D5 All 138
D6 All 134
D7 All 124
WRITE All 185
CS All 184
TDI All 183
TDO All 181
TMS All 2
TCK All 239
V
CCINT
All 16, 32, 43, 77, 88, 104,
137, 148, 164, 198, 214,
225
V
CCO
(The V
CCO
for the PQ/HQ240 package is common to all eight I/O
banks. Different output standards per I/O bank that require different
V
CCO
values cannot be supported.)
All 15, 30, 44, 61, 76, 90,
105, 121, 136, 150, 165,
180, 197, 212, 226, 240
QPro Virtex 2.5V QML High-Reliability FPGAs
18
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
R
V
REF
, Bank 0
(V
REF
pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all V
REF
pins are general I/O.
XQV100 ... + 229
XQV300 ... + 236
XQV600 ... + 230
V
REF
, Bank 1
(V
REF
pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all V
REF
pins are general I/O.
XQV100 ... + 194
XQV300 ... + 187
XQV600 ... + 193
V
REF
, Bank 2
(V
REF
pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all V
REF
pins are general I/O.
XQV100 ... + 168
XQV300 ... + 175
XQV600 ... + 169
V
REF
, Bank 3
(V
REF
pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all V
REF
pins are general I/O.
XQV100 ... + 133
XQV300 ... + 126
XQV600 ... + 132
V
REF
, Bank 4
(V
REF
pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all V
REF
pins are general I/O.
XQV100 ... + 108
XQV300 ... + 115
XQV600 ... + 109
V
REF
, Bank 5
(V
REF
pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all V
REF
pins are general I/O.
XQV100 ... + 73
XQV300 ... + 66
XQV600 ... + 72
V
REF
, Bank 6
(V
REF
pins are listed incrementally. Connect all pins listed for both
the required device and all smaller devices listed in the same
package.)
Within each bank, if input reference voltage is not required, all V
REF
pins are general I/O.
XQV100 ... + 47
XQV300 ... + 54
XQV600 ... + 48
Table 3:
Virtex QFP Package Pinout Information (Continued)
Pin Name Device PQ/HQ240
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

5962-9957201NNA

Mfr. #:
Buy 5962-9957201NNA
Manufacturer:
Xilinx
Description:
IC FPGA 2.5V HIREL VIRTEX 300
Lifecycle:
New from this manufacturer.
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