QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
www.xilinx.com
13
Preliminary Product Specification
1-800-255-7778
R
TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
Virtex Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Listed below are representative
values for typical pin locations and normal clock loading.
Values are expressed in nanoseconds unless otherwise
noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate,
with
DLL
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate,
without
DLL
Symbol Description
Speed Grade
Units
-4
Min Max
Combinatorial Delays
T
IO
IN input to OUT output - 0.0 ns
T
OFF
TRI input to OUT output high-impedance - 0.2 ns
T
ON
Tri input to valid data on OUT output - 0.2 ns
Symbol Description
Speed Grade
Units
-4
Min Max
T
TA PT CK
TMS and TDI setup times before TCK 4.0 - ns
T
TCKTAP
TMS and TDI hold times after TCK 2.0 - ns
T
TCKTDO
Output delay from clock TCK to output TDO - 11.0 ns
F
TCK
Maximum TCK clock frequency - 33 MHz
Symbol Description Device
Speed Grade
Units
-4
Min Max
LVTTL Global Clock Input to Output Delay using Output Flip-flop,
12 mA, Fast Slew Rate,
with
DLL. For data
output
with different
standards, adjust the delays with the values shown in "IOB Output
Switching Characteristics Standard Adjustments" on page 8.
XQV100 - 3.6 ns
XQV300 - 3.6 ns
XQV600 - 3.6 ns
XQV1000 - 3.6 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% V
CC
threshold with 35 pF external capacitive load. For different loads, see Ta b l e 2 .
3. DLL output jitter is already included in the timing calculation.
Symbol Description Device
Speed Grade
Units
-4
Min Max
LVTTL Global Clock Input to Output Delay using Output Flip-flop,
12 mA, Fast Slew Rate,
without
DLL. For data
output
with different
standards, adjust the delays with the values shown in "IOB Output
Switching Characteristics Standard Adjustments" on page 8.
XQV100 - 5.7 ns
XQV300 - 5.9 ns
XQV600 - 6.0 ns
XQV1000 - 6.3 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% V
CC
threshold with 35 pF external capacitive load. For different loads, see Ta b l e 2 .
