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5962-9957201NNA

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
www.xilinx.com
7
Preliminary Product Specification
1-800-255-7778
R
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in "IOB Output Switching Characteristics Standard Adjustments" on page 8.
Symbol Description
Speed Grade
Units
-4
Min Max
Propagation Delays
T
IOOP
O input to pad - 3.5 ns
T
IOOLP
O input to pad via transparent latch - 4.0 ns
3-State Delays
T
IOTHZ
T input to pad high-impedance
(1)
-2.4ns
T
IOTON
T input to valid data on pad - 3.7 ns
T
IOTLPHZ
T input to pad high-impedance via transparent latch
(1)
-3.0ns
T
IOTLPON
T input to valid data on pad via transparent latch - 4.2 ns
T
GTS
GTS to pad high-impedance
(1)
-6.3ns
Sequential Delays
T
IOCKP
Clock CLK to pad - 3.5 ns
T
IOCKHZ
Clock CLK to pad high-impedance (synchronous)
(1)
-2.9ns
T
IOCKON
Clock CLK to valid data on pad (synchronous) - 4.1 ns
Setup and Hold Times before/after Clock CLK Setup Time / Hold Time
(2)
T
IOOCK
/T
IOCKO
O input 1.3 / 0 - ns
T
IOOCECK
/T
IOCKOCE
OCE input 1.0 / 0 - ns
T
IOSRCKO
/T
IOCKOSR
SR input (OFF) 1.4 / 0 - ns
T
IOTCK
/T
IOCKT
3-state setup times, T input 0.9 / 0 - ns
T
IOTCECK
/T
IOCKTCE
3-state setup times, TCE input 1.1 / 0 - ns
T
IOSRCKT
/T
IOCKTSR
3-state setup times, SR input (TFF) 1.3 / 0 - ns
Set/Reset Delays
T
IOSRP
SR input to pad (asynchronous) 4.6 - ns
T
IOSRHZ
SR input to pad high-impedance (asynchronous)
(1)
3.9 - ns
T
IOSRON
SR input to valid data on pad (asynchronous) 5.1 - ns
Notes:
1. High-impedance turn-off delays should not be adjusted.
2. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
QPro Virtex 2.5V QML High-Reliability FPGAs
8
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
R
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Symbol Description Standard
Speed Grade
Units-4
Output Delay Adjustments
T
OLVTTL_S2
Standard-specific adjustments for output delays
terminating at pads (based on standard capacitive
load, C
sl
)
LVTTL, slow 2 mA 17.0 ns
T
OLVTTL_S4
4 mA 8.6 ns
T
OLVTTL_S6
6 mA 5.6 ns
T
OLVTTL_S8
8 mA 3.5 ns
T
OLVTTL_S12
12 mA 2.2 ns
T
OLVTTL_S16
16 mA 2.0 ns
T
OLVTTL_S24
24 mA 1.6 ns
T
OLVTTL_F2
LVTTL, fast 2 mA 15.1 ns
T
OLVTTL_F4
4 mA 6.1 ns
T
OLVTTL_F6
6 mA 3.6 ns
T
OLVTTL_F8
8 mA 1.2 ns
T
OLVTTL_F12
12 mA 0.0 ns
T
OLVTTL_F16
16 mA –0.05 ns
T
OLVTTL_F24
24 mA –0.23 ns
T
OLVCMOS2
LVCM OS 2 0.1 2 ns
T
OPCI33_3
PCI, 33 MHz, 3.3V 2.7 ns
T
OPCI33_5
PCI, 33 MHz, 5.0V 3.3 ns
T
OGTL
GTL 0.6 ns
T
OGTLP
GTL+ 1.0 ns
T
OHSTL_I
HSTL I –0.5 ns
T
OHSTL_III
HSTL III –1.0 ns
T
OHSTL_IV
HSTL IV –1.1 ns
T
OSSTL2_I
SSTL2 I –0.5 ns
T
OSSTL2_II
SSTL2 II –1.0 ns
T
OSSTL3_I
SSTL3 I –0.5 ns
T
OSSTL3_II
SSTL3 II –1.1 ns
T
OCTT
CTT –0.6 ns
T
OAGP
AGP –1.0 ns
QPro Virtex 2.5V QML High-Reliability FPGAs
DS002 (v1.5) December 5, 2001
www.xilinx.com
9
Preliminary Product Specification
1-800-255-7778
R
Calculation of T
ioop
as a Function of Capacitance
The values for T
ioop
were based on the standard capacitive
load (Csl) for each I/O standard as listed in Ta b l e 2 .
For other capacitive loads, use the formulas below to calcu-
late the corresponding T
ioop
:
T
ioop
= T
ioopl
+ T
opadjust
+
(C
load
- C
sl
) * fl
Where:
T
opadjust
is reported above in the Output Delay
Adjustment section.
C
load
is the capacitive load for the design.
Clock Distribution Guidelines and Switching Characteristics
Table 2:
Constants for Use in Calculation of T
op
Standard C
sl
(pF) fl (ns/pF)
LVTTL slow
slew rate
2 mA drive 35 0.41
4 mA drive 35 0.20
6 mA drive 35 0.100
8 mA drive 35 0.086
12 mA drive 35 0.058
16 mA drive 35 0.050
24 mA drive 35 0.048
LVTTL fast
slew rate
2 mA drive 35 0.41
4 mA drive 35 0.20
6 mA drive 35 0.13
8 mA drive 35 0.079
12 mA drive 35 0.044
16 mA drive 35 0.043
24 mA drive 35 0.033
LVCMOS2 35 0.041
PCI 33 MHz 5V 50 0.050
PCI 33 MHZ 3.3V 10 0.050
GTL 0 0.014
GTL+ 0 0.017
HSTL Class I 20 0.022
HSTL Class III 20 0.016
HSTL Class IV 20 0.014
SSTL2 Class I 30 0.028
SSTL2 Class II 30 0.016
SSTL3 Class 1 30 0.029
SSTL3 Class II 30 0.016
CTT 20 0.035
AGP 10 0.037
Table 2:
Constants for Use in Calculation of T
op
Standard C
sl
(pF) fl (ns/pF)
Symbol Description Device
Speed Grade
Units
-4
Min Max
Global Clock Skew
T
GSKEWIOB
Global clock skew between IOB flip-flops XQV100 - 0.15 ns
XQV300 - 0.18 ns
XQV600 - 0.17 ns
XQV1000 - 0.25 ns
T
GPIO
Global clock PAD to output All - 0.9 ns
T
GIO
Global clock buffer I input to O output All - 0.9 ns
Notes:
1. These clock-distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under
worst-case conditions. Precise values for a particular design are provided by the timing analyzer.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

5962-9957201NNA

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Buy 5962-9957201NNA
Manufacturer:
Xilinx
Description:
IC FPGA 2.5V HIREL VIRTEX 300
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