LTC6803-1/LTC6803-3
10
680313fa
PIN FUNCTIONS
V
REG
(Pin 34 on LTC6803-1/ Pin 35 on LTC6803-3 ): Linear
Voltage Regulator Output. This pin should be bypassed
with a 1µF capacitor. The V
REG
pin is capable of supply-
ing up to 4mA to an external load. The V
REG
pin does not
sink current.
TOS (Pin 35 on LTC6803-1/Pin 36 on LTC6803-3): Top
of Stack Input. Tie TOS to V
REG
when the LTC6803-1 or
LTC6803-3 is the top device in a daisy chain. Tie TOS to
V
–
otherwise. When TOS is tied to V
REG
, the LTC6803-1
or LTC6803-3 ignores the SDOI input and SCKO, CSBO
are turned off. When TOS is tied to V
–
, the LTC6803-1
or LTC6803-3 expects data to be passed to and from the
SDOI pin.
NC (Pin 36 on LTC6803-1 ): No Connection.
WDTB (Pin 37): Watchdog Timer Output (Active Low). If
there is no valid command received for 1 to 2.5 seconds, the
WDTB output is asserted. The WDTB pin is an open-drain
NMOS output. When asserted it pulls the output down to
V
–
and resets the configuration register to its default state.
GPIO1, GPIO2 (Pins 38, 39): General Purpose Input/
Output. By writing a “0” to a GPIO configuration register
bit, the open-drain output is activated and the pin is pulled
to V
–
. By writing logic “1” to the configuration register bit,
the corresponding GPIO pin is high impedance. An external
resistor is required to pull the pin up to V
REG
. By reading
the configuration register locations GPIO1 and GPIO2, the
state of the pins can be determined. For example, if a “0”
is written to register bit GPIO1, a “0” is always read back
because the output N-channel MOSFET pulls Pin 38 to V
–
.
If a “1” is written to register bit GPIO1, the pin becomes
high impedance. Either a “1” or a “0” is read back, depend-
ing on the voltage present at Pin 38. The GPIOs makes it
possible to turn on/off circuitry around the LTC6803, or
read logic values from a circuit around the LTC6803. The
GPIO pins should be connected to V
–
if not used.
V
MODE
(Pin 40): Voltage Mode Input. When V
MODE
is tied
to V
REG
, the SCKI, SDI, SDO and CSBI pins are configured
as voltage inputs and outputs. This means these pins
accept standard TTL logic levels. Connect V
MODE
to V
REG
when the LTC6803-1 or LTC6803-3 is the bottom device in
a daisy chain. When V
MODE
is connected to V
–
, the SCKI,
SDI and CSBI pins are configured as current inputs and
outputs, and SDO is unused. Connect V
MODE
to V
–
when
the LTC6803-1 or LTC6803-3 is being driven by another
LTC6803-1 or LTC6803-3 in a daisy chain.
SCKI (Pin 41): Serial Clock Input. The SCKI pin interfaces
to any logic gate (TTL levels) if V
MODE
is tied to V
REG
. SCKI
must be driven by the SCKO pin of another LTC6803-1 or
LTC6803-3 if V
MODE
is tied to V
–
. See Serial Port in the
Applications Information Section.
SDI (Pin 42): Serial Data Input. The SDI pin interfaces to
any logic gate (TTL levels) if V
MODE
is tied to V
REG
. SDI
must be driven by the SDOI pin of another LTC6803-1 or
LTC6803-3 if V
MODE
is tied to V
–
. See Serial Port in the
Applications Information section.
SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS
open-drain output if V
MODE
is tied to V
REG
. A pull-up resis-
tor is needed on SDO. SDO is not used if V
MODE
is tied to
V
–
. See Serial Port in the Applications Information section.
CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI
pin interfaces to any logic gate (TTL levels) if V
MODE
is tied
to V
REG
. CSBI must be driven by the CSBO pin of another
LTC6803-1 or LTC6803-3 if V
MODE
is tied to V
–
. See Serial
Port in the Applications Information section.
