LTC6803-1/LTC6803-3
34
680313fa
APPLICATIONS INFORMATION
Figure 22. Providing an Isolated High Speed Data Interface
the resistive loading on the cell group when the IC enters
standby mode (i.e., when WDTB goes low). An LT6004
micropower operational amplifier section is shown for
buffering the divider signal to preserve accuracy. This
circuit has the virtue that it can be converted about four
times more frequently than the entire battery array, thus
offering a higher sample rate option at the expense of
some precision/accuracy, reserving the high resolution
cell readings for calibration and balancing data.
PROVIDING HIGH SPEED ISOLATION OF THE SPI DATA
PORT
Isolation techniques that are capable of supporting the
1Mbps data rate of the LTC6803 require more power on
the isolated (battery) side than can be furnished by the
V
REG
output of the LTC6803. To keep battery drain minimal,
this means that a DC/DC function must be implemented
along with a suitable data isolation circuit, such as shown
in Figure 22. A quad (3 + 1) data isolator Si8441AB-C-IS
is used to provide non-galvanic SPI signal connections
between a host microprocessor and an LTC6803. An
inexpensive isolated DC/DC converter provides power-
V
DD1
GND1
A1
A2
A3
A4
EN1
GND1
V
DD2
GND2
B1
B2
B3
B4
EN2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Si8441AB-C-IS
QUAD ISOLATOR
1k
4.22k
V
REG
SDO
SCKI
CSB1
SCI
V
–
1µF1µF
BAT54S
CMDSH2-3
6
PE-68386
33nF
• •
4
1
3
12
13
1/4 74ABT126
11
2
1
1/4 74ABT126
3
5
4
1/4 74ABT126
6
8
10
1/4 74ABT126
74ABT126 SUPPLY SHARED WITH
ISOLATOR V
DD2
and GND2
9
4.22k
4.22k
4.22k
680313 F22
1µF
470pF
IN1
GND1
IN2
GND2
8
7
6
5
1
2
3
4
V
CC1
OUT1
V
CC2
OUT2
LTC1693-2
20.0k
100Ω
5V_HOST
100Ω
100Ω
100Ω
10.0k
SPI_CLOCK
SPI_CHIPSELECT
SPI_MASTEROUT
SPI_MASTERIN
GND_HOST
ing of the isolator function completely from the host 5V
power supply. A quad three-state buffer is used to allow
SPI inputs at the LTC6803 to rise to logic high level when
the isolator circuitry powers down, assuring the lowest
power consumption in the standby condition. The pull-
ups to V
REG
are selected to match the internal loading on
V
REG
by ICs operating with a current mode SPI interface,
thus balancing the current in all cells during operation.
The additional pull-up on the SDO line (1k resistor and
Schottky diode) is to improve rise time, in lower data-rate
applications this may not be needed.
SUPPLY DECOUPLING IF BATTERY-STACK POWERED
As shown in Figure 23, the LTC6803-3 can have filtering
on both V
+
and V
–
, so differential bypassing to the cell
group potentials is recommended. The Zener suppresses
overvoltages from reaching the IC supply pins. A small
ferrite-bead inductor provides protection for the Zener, par-
ticularly from energetic ESD strikes. Since the LTC6803-1
cannot have a series resistance to V
–
, additional Schottky
diodes are needed to prevent ESD-induced reverse-supply
(substrate) currents to flow.
