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LTC6803IG-3#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
LTC6803-1/LTC6803-3
31
680313fa
Figure 14. Reverse-Voltage Protection for
the Daisy Chain (One Link Connection Shown)
APPLICATIONS INFORMATION
situation might occur in a modular battery system during
initial installation or a service procedure. The daisy-chain
ports are protected from the reverse potential in this sce-
nario by external series high voltage diodes required in
the upper port data connections as shown in Figure 14.
During the charging phase of operation, this fault would
lead to forward biasing of daisy-chain ESD clamps that
would also lead to part damage. An alternative connection
to carry current during this scenario will avoid this stress
from being applied (Figure 14).
Internal Protection Diodes
Each pin of the LTC6803 has protection diodes to help
prevent damage to the internal device structures caused
by external application of voltages beyond the supply rails
as shown in Figure 15. The diodes shown are conventional
silicon diodes with a forward breakdown voltage of 0.5V.
The unlabeled Zener diode structures have a reverse-
breakdown characteristic which initially breaks down at
12V then snaps back to a 7V clamping potential. The Zener
diodes labeled Z
CLAMP
are higher voltage devices with an
initial reverse breakdown of 30V snapping back to 25V.
The forward voltage drop of all Zeners is 0.5V. Refer to
Figure 15 in the event of unpredictable voltage clamping
or current flow. Limiting the current flow at any pin to
±10mA will prevent damage to the IC.
+
+
RSO7J
×3
LTC6803-1
(NEXT HIGHER IN STACK)
SDI SCKI CSBISDO
V
–
OPTIONAL
REDUNDANT
CURRENT
PATH
PROTECT
AGAINST
BREAK
HERE
LTC6803-1
(NEXT LOWER IN STACK)
SDOI SCKO CSBO
V
+
860313 F14
Figure 15. Internal Protection Diodes
6
S12
5
C12
4
V
+
7
C11
3
SCKO
2
SDOI
8
S11
9
C10
Z
CLAMP
LTC6803-3
Z
CLAMP
Z
CLAMP
Z
CLAMP
Z
CLAMP
Z
CLAMP
Z
CLAMP
Z
CLAMP
Z
CLAMP
NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 30
10
S10
11
C9
12
S9
13
C8
14
S8
15
C7
16
S7
17
C6
18
S6
19
C5
20
S5
21
C4
22
S4
23
C3
24
S3
25
C2
26
S2
27
C1
28
S1
29
30
C0
V
–
1
CSBO
44
CSBI
43
SDO
42
SDI
41
SCKI
35
V
REG
V
REF
V
TEMP2
V
TEMP1
34
33
40
V
MODE
39
GPIO2
38
GPIO1
37
WDTB
36
TOS
680313 F15
32
READING EXTERNAL TEMPERATURE PROBES
The LTC6803 includes two channels of ADC input, V
TEMP1
and V
TEMP2
, that are intended to monitor thermistors
(tempco about –4%/°C generally) or diodes (–2.2mV/°C
typical) located within the cell array. Sensors can be
powered directly from V
REF
as shown in Figure 16 (up to
60µA total).
LTC6803-1/LTC6803-3
32
680313fa
APPLICATIONS INFORMATION
Figure 16. Driving Thermistors Directly from V
REF
Figure 17. Buffering V
REF
for Higher Current Sensors
Figure 18. Expanding Sensor Count with Multiplexing
For sensors that require higher drive currents, a buffer
op amp may be used as shown in Figure 17. Power for
the sensor is actually sourced indirectly from the V
REG
pin in this case. Probe loads up to about 1mA maximum
are supported in this configuration. Since V
REF
is shut-
down during the LTC6803 idle and shutdown modes, the
thermistor drive is also shut off and thus power dissipation
minimized. Since V
REG
remains always on, the buffer op
amp (LT6000 shown) is selected for its ultralow power
consumption (12µA).
Expanding Probe Count
As shown Figure 18, a dual 4:1 multiplexer is used to ex-
pand the general purpose V
TEMP1
and V
TEMP2
ADC inputs
to accept 8 different probe signals. The channel is selected
by setting the general purpose digital outputs GPIO1 and
GPIO2 and the resultant signals are buffered by sections
of the LT6004 micropower dual operational amplifier. The
probe excitation circuitry will vary with probe type and is
not shown here.
Another method of multiple sensor support is possible
without the use of any GPIO pins. If the sensors are PN
diodes and several used in parallel, then the hottest diode
will produce the lowest forward voltage and effectively
establish the input signal to the V
TEMP
input(s). The hottest
diode will therefore dominate the readout from the V
TEMP
inputs that the diodes are connected to. In this scenario,
the specific location or distribution of heat is not known,
but such information may not be important in practice.
Figure 19 shows the basic concept. In any of the sensor
configurations shown, a full-scale cold readout would be
an indication of a failed open-sensor connection to the
LTC6803.
Figure 19. Using Diode Sensors as Hot Spot Detectors
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
–
LTC6803-1
1µF
680313 F16
1µF
100k
NTC
100k 100k
100k
NTC
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
–
LTC6803-1
680313 F17
10k
NTC
10k 10k
10k
NTC
–
+
LT6000
6
4 8
7
1
8
3
2
1µF
680313 F18
4
1/2 LT6004
1/2 LT6004
+
–
+
–
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y0
Y2
Y
Y3
Y1
INH
V
EE
GND
PROBE8
PROBE7
PROBE6
PROBE5
PROBE4
PROBE3
PROBE2
PROBE1
CPO2
GPO1
V
REG
V
TEMP2
V
TEMP1
V
–
V
CC
X2
X1
X
X0
X3
A
B
74HC4052
5
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
–
LTC6803-1
200k
680313 F19
200k
LTC6803-1/LTC6803-3
33
680313fa
APPLICATIONS INFORMATION
ADDING CALIBRATION AND FULL-STACK
MEASUREMENTS
The general purpose V
TEMP
ADC inputs may be used to digi-
tize any signals from 0V to 4V with accuracy corresponding
closely with that of the cell 1 ADC input. One useful signal
to provide is a high accuracy voltage reference, such as
3.300V from an LTC6655-3.3. From periodic readings of
this signal, the host software can provide correction of
the LTC6803 readings to improve the accuracy over that
of the internal LTC6803 reference and/or validate ADC
operation. Figure 20 shows a means of selectively pow-
ering an LTC6655-3.3 from the battery stack, under the
control of the GPIO1 output of the LTC6803-1. Since the
operational power of the reference IC would add significant
Figure 20. Providing Measurement of Calibration Reference
GPIO1
38
V
REG
34
V
TEMP1
31
V
–
29
1M
TOP CELL POTETNTIAL
Si2351DS 100nF
LTC6803-1
SHDN
V
IN
GND
GND
GND
V
OUT_F
V
OUT_S
GND
1
2
3
4
8
7
6
5
1µF 10µF
680313 F20
LTC6655-3.3
CZT5551
Figure 21. Using a V
TEMP
Input for Full-Stack Readings
–
+
1/2 LT6004
V
TEMP1
V
REG
WDTB
V
–
CELL GROUP
–
CELL GROUP
+
1
3
3
1
2
2N7002K
1µF
10nF
680313 F21
31.6k
2
4
8
499k
1M
thermal loading to the LTC6803 if powered from V
REG
, an
external high voltage NPN pass transistor is used to form
a local 4.4V (V
be
below V
REG
) from the battery stack. The
GPIO1 signal controls a PMOS FET switch to activate the
reference when calibration is to be performed. Since GPIO
signals default to logic high in shutdown, the reference
will automatically turn off during idle periods.
Another useful signal is a measure of the total stack poten-
tial. This provides a redundant operational measurement
of the cells in the event of a malfunction in the normal
acquisition process, or as a faster means of monitoring
the entire stack potential. Figure 21 shows how a resis-
tive divider is used to derive a scaled representation of a
full cell group potential. A MOSFET is used to disconnect
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

LTC6803IG-3#TRPBF

Mfr. #:
Buy LTC6803IG-3#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Daisy Chain SPI
Lifecycle:
New from this manufacturer.
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