LTC6803-1/LTC6803-3
28
680313fa
APPLICATIONS INFORMATION
between C2 and C4 after several cycles of measuring cells
B3 and B4. Thus the measurements for B3 and B4 may
indicate a valid cell voltage when in fact the exact state of
B3 and B4 is unknown.
To reliably detect an open connection, the command
STOWAD is provided. With this command, two 100µA
current sources are connected to the ADC inputs and
turned on during all cell conversions. Referring again to
Figure 11, with the STOWAD command, the C3 pin will be
pulled down by the 100µA current source during the B3
cell measurement and during the B4 cell measurement.
This will tend to decrease the B3 measurement result and
increase the B4 measurement result relative to the normal
STCVAD command. The biggest change is observed in the
B4 measurement when C3 is open. So, the best method to
detect an open wire at input C3 is to look for an increase
Figure 10. Open Connection
Figure 11. Open Connection with RC Filtering
in the value of battery connected between inputs C3 and
C4 (battery B4).
The following algorithm can be used to detect an open
connection to cell pin Cn:
1. Issue a STOWAD command (with 100µA sources
connected).
2. Issue a RDCV command and store all cell measurements
into array CELLA(n).
3. Issue the 2nd STOWAD command (with 100µA sources
connected).
4. Issue the 2nd RDCV command and store all cell mea-
surements into array CELLB(n).
5. For battery cells, if CELLA(1) < 0 or CELLB(1) < 0, V
must be open.
If CELLA(12) < 0 or CELLB(12) < 0, C12 must be open.
For n = 2 to 11, if CELLB(n+1) – CELLA(n+1) > 200mV,
or CELLB(n+1) reaches the full scale of 5.375V, then
Cn is open.
The 200mV threshold is chosen to provide tolerance for
measurement errors. For a system with the capacitor con-
nected to Cn larger than 0.5µF, repeating step 3 several
times will discharge the external capacitor enough to meet
the criteria.
If the top C pin is open yet V
+
is still connected, then the
best way to detect an open connection to the top C pin
is by comparing the sum of all cell measurements using
the STCVAD command to an auxiliary measurement of
the sum of all the cells, using a method similar to that
shown in Figure 21. A significantly lower result for the
sum of all 12 cells suggests an open connection to the
top C pin, provided it was already determined that no
other C pin is open.
USING THE S PINS AS DIGITAL OUTPUTS OR
GATE DRIVERS
The S outputs include an internal pull-up PMOS. Therefore
the S pins will behave as a digital output when loaded with
a high impedance, e.g., the gate of an external MOSFET.
For applications requiring high battery discharge currents,
connect a discrete PMOS switch device and suitable
+
+
+
+
+
100µA
MUX
C2
25
C3
23
C4
B4
B3
680313 F10
LTC6803-1
21
V
29
C1
27
+
+
+
+
+
100µA
MUX
C2
25
C3
23
C4
B4 C
F4
C
F3
B3
680313 F11
LTC6803-1
21
V
29
C1
27
LTC6803-1/LTC6803-3
29
680313fa
APPLICATIONS INFORMATION
discharge resistor to the cell, and the gate terminal to the
S output pin, as illustrated in Figure 12.
Figure 12. External Discharge FET Connection (One Cell Shown)
POWER DISSIPATION AND THERMAL SHUTDOWN
The MOSFETs connected to the pins S1 through S12 can be
used to discharge battery cells. An external resistor should
be used to limit the power dissipated by the MOSFETs. The
maximum power dissipation in the MOSFETs is limited by
the amount of heat that can be tolerated by the LTC6803.
Excessive heat results in elevated die temperatures. The
electrical characteristics for the LTC6803 I-grade are
guaranteed for die temperatures up to 85°C. Little or no
degradation will be observed in the measurement accuracy
for die temperatures up to 105°C. Damage may occur
above 150°C, therefore the recommended maximum die
temperature is 125°C.
To protect the LTC6803 from damage due to overheating,
a thermal shutdown circuit is included. Overheating of the
device can occur when dissipating significant power in the
cell discharge switches. The problem is exacerbated when
the thermal conductivity of the system is poor.
The thermal shutdown circuit is enabled whenever the
device is not in standby mode (see Modes of Operation).
It will also be enabled when any current mode input or
output is sinking or sourcing current. If the temperature
detected on the device goes above approximately 145°C,
the configuration registers will be reset to default states,
turning off all discharge switches and disabling ADC
conversions. When a thermal shutdown has occurred, the
THSD bit in the temperature register group will go high.
The bit is cleared by performing a read of the temperature
registers (RDTMP command).
Since thermal shutdown interrupts normal operation, the
internal temperature monitor should be used to determine
when the device temperature is approaching unacceptable
levels.
USING THE LTC6803 WITH LESS THAN 12 CELLS
If the LTC6803 is powered by the stacked cells, the minimum
number of cells is governed by the supply voltage require-
ments of the LTC6803. The sum of the cell voltages must be
10V to guarantee that all electrical specifications are met.
Figure 13 shows an example of the LTC6803 when used to
monitor seven cells. The lowest C inputs connect to the-
seven cells and the upper C inputs connect to C12. Other
configurations, e.g., 9 cells, would be configured in the
same way: the lowest C inputs connected to the battery
cells and the unused C inputs connected to C12. The unused
inputs will result in a reading of 0V for those channels.
The ADC can also be commanded to measure a stack of
10 or 12 cells, depending on the state of the CELL10 bit
in the control register. The ADC can also be commanded
to measure any individual cell voltage.
FAULT PROTECTION
Care should always be taken when using high energy
sources such as batteries. There are numerous ways
that systems can be misconfigured when considering
the assembly and service procedures that might affect a
battery system during its useful lifespan. Table 15 shows
the various situations that should be considered when plan-
ning protection circuitry. The first five scenarios are to be
anticipated during production and appropriate protection
is included within the LTC6803-1/LTC6803-3 device itself.
BATTERY INTERCONNECTION INTEGRITY
The FMEA scenarios involving a break in the stack of battery
cells are potentially the most damaging. In the case where
the battery stack has a discontinuity between groupings
of cells monitored by LTC6803 ICs, any load will force a
large reverse potential on the daisy-chain connection. This
+
680313 F12
C (n)
C (n – 1)
S (n)
3.3k
33Ω
1W
Si2351DS
LTC6803-1/LTC6803-3
30
680313fa
APPLICATIONS INFORMATION
Figure 13. Monitoring 7 Cells with the LTC6803-1/LTC6803-3
Table 15. LTC6803-1/LTC6803-3 Failure Mechanism Effect Analysis
SCENARIO EFFECT DESIGN MITIGATION
Cell input open-circuit (random). Power-up sequence at IC inputs. Clamp diodes at each pin to V
+
and V
(within IC) provide
alternate power path.
Cell input open-circuit (random). Differential input voltage overstress. Zener diodes across each cell voltage input pair (within IC)
limits stress.
Disconnection of a harness
between a group of battery cells
and the IC (in a system of stacked
groups).
Loss of supply connection to the IC. Separate power may be supplied by a local supply.
Data link disconnection between
stacked LTC6803 units.
Break of "daisy-chain" communication (no stress to
ICs). Communication will be lost to devices above the
disconnection. The devices below the disconnection
are still able to communicate and perform all functions,
however, the polling feature is disabled.
All units above the disconnection will enter standby mode
within 2 seconds of disconnect. Discharge switches are
disabled in standby mode.
Cell-pack integrity, break between
stacked units.
Daisy-chain voltage reversal up to full stack potential
during pack discharge.
Use series protection diodes with top-port I/O connections
(RS07J for up to 600V). Use isolated data link at bottom-
most data port.
Cell-pack integrity, break between
stacked units.
Daisy-chain positive overstress during charging. Add redundant current path link. See Figure 14.
Cell-pack integrity, break within
stacked unit.
Cell input reverse overstress during discharge. Add parallel Schottky diodes across each cell for load-
path redundancy. Diode and connections must handle full
operating current of stack, will limit stress on IC.
Cell-pack integrity, break within
stacked unit.
Cell input positive overstress during charge. Add SCR across each cell for charge-path redundancy. SCR
and connections must handle full charging current of stack,
will limit stress on IC by selection of trigger Zener.
+
+
+
+
+
+
+
V
+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
V
LTC6803-1
100 100
NEXT HIGHER GROUP
OF 7 CELLS
NEXT LOWER GROUP
OF 7 CELLS
+
+
+
+
+
+
+
V
+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
C0
V
LTC6803-3
NEXT HIGHER GROUP
OF 7 CELLS
NEXT LOWER GROUP
OF 7 CELLS
680313 F13

LTC6803IG-3#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Daisy Chain SPI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union