LTC6803-1/LTC6803-3
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OPERATION
Table 13. Memory Bit Descriptions (continued)
NAME DESCRIPTION VALUES
MCxI Mask Cell x Interrupts
x = 1..12 0 = enable interrupts for cell ‘x’ (default)
1 = turn off interrupts and clear flags for cell ‘x’
CxV Cell x Voltage*
x = 1..12 12-bit ADC measurement value for cell ‘x’
cell voltage for cell ‘x’ = (CxV – 512) • 1.5mV
reads as 0xFFF while A/D conversion in progress
CxUV Cell x Undervoltage Flag
x = 1..12 cell voltage compared to V
UV
comparison voltage
0 = cell ‘x’ not flagged for undervoltage condition; 1 = cell ‘x’ flagged
CxOV Cell x Overvoltage Flag
x = 1..12 cell voltage compared to V
OV
comparison voltage
0 = cell ‘x’ not flagged for overvoltage condition; 1 = cell ‘x’ flagged
ETMPx External Temperature Measurement* Temperature measurement voltage = (ETMPx – 512) • 1.5mV
THSD Thermal Shutdown Status
0 = thermal shutdown has not occurred; 1 = thermal shutdown has occurred
Status cleared to ‘0’ on read of Thermal Register Group
REV Revision Code Device revision code
ITMP Internal Temperature Measurement* Temperature measurement voltage = (ITMP – 512) • 1.5mV = 8mV * T(°K)
PEC Packet Error Code Cyclic redundancy check (CRC) value
REF Reference Voltage for Diagnostics This reference voltage = (REF – 512) • 1.5mV. Normal range is within 2.1V to 2.9V
*Voltage equations use the decimal value of the registers, 0 to 4095 for 12-bit and 0 to 255 for 8-bit registers
SERIAL COMMAND EXAMPLES
Examples below use a configuration of three stacked
LTC6803-1 or LTC6803-3 devices: bottom (B), middle
(M), and top (T)
Write Configuration Registers (Figure 8)
1. Pull CSBI low
2. Send WRCFG command and its PEC byte
3. Send CFGR0 byte for top device, then CFGR1 (T), …CFGR5 (T), PEC of CFGR0(T) to CFGR5(T)
4. Send CFGR0 byte for middle device, then CFGR1 (M) … CFGR5 (M) ), PEC of CFGR0(M) to CFGR5(M)
5. Send CFGR0 byte for bottom device, then CFGR1 (B), … CFGR5 (B) ), PEC of CFGR0(B) to CFGR5(B)
6. Pull CSBI high; data latched into all devices on rising edge of CSBI. S pins respond as data latched.
Calculation of serial interface time for sequence above:
Number of devices in stack = N
Number of bytes in sequence = B = 2 command byte and 7 data bytes per device = 2 + 7 • N
Serial port frequency per bit = F
Time = (1/F) • B • 8 bits/byte = (1/F) • (2 + 7 • N) • 8
Time for 3-cell example above, with 1MHz serial port = (1/1000000) • (2 + 7 • 3) • 8 = 184µs
LTC6803-1/LTC6803-3
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OPERATION
Read Cell Voltage Registers (12 Cell Mode)
1. Pull CSBI low
2. Send RDCV command and PEC
3. Read CVR00 byte of bottom device, then CVR01 (B), CVR02 (B), … CVR17 (B), and then PEC (B)
4. Read CVR00 byte of middle device, then CVR01 (M), CVR02 (M), … CVR17 (M), and then PEC (M)
5. Read CVR00 byte for top device, then CVR01 (T), CVR02 (T), … CVR17 (T), and then PEC (T)
6. Pull CSBI high
Calculation of serial interface time for sequence above:
Number of devices in stack = N
Number of bytes in sequence = B = 2 command byte, and 18 data bytes plus 1 PEC byte per device = 2 + 19 • N
Serial port frequency per bit = F
Time = (1/F) • B • 8 bits/byte = (1/F) • (2 + 19 • N) • 8
Time for 3-cell example above, with 1MHz serial port = (1/1000000) • (2 + 19 • 3) • 8 = 472µs
Start Cell Voltage ADC Conversions and Poll Status (Toggle Polling)
1. Pull CSBI low
2. Send STCVAD command byte and PEC (all devices in stack start ADC conversions simultaneously)
3. SDO output from bottom device pulled low for approximately 12ms
4. SDO output toggles at 1kHz rate, indicating conversions complete for all devices in daisy chain
5. Pull CSBI high to exit polling
Start Cell Voltage ADC Conversions and Poll Status (Broadcast Command with Toggle Polling)
1. Pull CSBI low
2. Send STCVAD command and PEC (all devices in stack start ADC conversions simultaneously)
3. SDO output of all devices in parallel pulled low for approximately 12ms
4. SDO output toggles at 1kHz rate, indicating conversions complete for all devices in the daisy chain
5. Pull CSBI high to exit polling
Poll Interrupt Status (Level Polling)
1. Pull CSBI low
2. Send PLINT command and PEC
3. SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high
4. Pull CSBI high to exit polling
Figure 8. S Pin Action and SPI Transmission
CSBI
SCKI
SDI
Sn
(n = 1 TO 12)
Sn, DISCHARGE PIN STATE
t
d
< 2µs IF Sn IS UNLOADED
t
d
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WRCFG + CFGR + PEC
LTC6803-1/LTC6803-3
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APPLICATIONS INFORMATION
DIFFERENCE BETWEEN THE LTC6803-1 AND LTC6803-3
The only difference between the LTC6803-1 and the
LTC6803-3 is the bonding of the V
and C0 pins. The
V
and C0 are separate signals on every LTC6803 die.
In the LTC6803-1 package, the V
and C0 signals are
shorted together by bonding these signals to the same
pin. In the LTC6803-3 package, V
and C0 are separate
pins. Therefore, the LTC6803-1 is pin compatible with the
LTC6802-1. For new designs the LTC6803-3 pinout allows
a Kelvin connection to C0 (Figure 24).
CELL VOLTAGE FILTERING
The LTC6803 employs a sampling system to perform its
analog-to-digital conversions and provides a conversion
result that is essentially an average over the 0.5ms con-
version window, provided there isn’t noise aliasing with
respect to the delta-sigma modulator rate of 512kHz. This
indicates that a lowpass filter with 30dB attenuation at
500kHz may be beneficial. Since the delta-sigma integra-
tion bandwidth is about 1kHz, the filter corner need not
be lower than this to assure accurate conversions.
Series resistors of 100Ω may be inserted in the input
paths without introducing meaningful measurement er-
ror. Shunt capacitors may be added from the cell inputs
to V
, creating RC filtering as shown in Figure 9. The cell
balancing MOSFET in Figure 12 can cause a small transient
when it switches on and off. Keeping the cutoff frequency
of the RC filter relatively high will allow adequate settling
prior to the actual conversion. A delay of about 500µs is
provided in the ADC timing, so a 16kHz LPF is optimal
(100Ω, 0.1µF) and offers 30dB of noise rejection.
Larger series resistors and shunt capacitors can be used
to lower the filter bandwidth. The measurement error due
to the larger component values is a complex function of
the component values. The error also depends on how
often measurements are made. Table 14 is an example.
In each example a 3.6V cell is being measured and the
error is displayed in millivolts. There is a RC filter in series
with inputs C1 through C12 for the LTC6803-1. There is
an RC filter in series with inputs C0 through C12 for the
LTC6803-3.
Table 14. Cell Measurement Errors vs Input RC Values
R = 100Ω,
C = 0.1µF
R = 1k,
C = 0.1µF
R = 1k,
C = 1µF
R = 10k,
C = 3.3µF
Cell 1 Error
(mV, LTC6803-1)
0.5 4.5 1.5 1.5
Cell 2 to Cell 12 (mV) 1 9 3 0.5
For the LTC6803-1, no resistor should be placed in series
with the V
pin. Because the supply current flows from
the V
pin, any resistance on this pin could generate a
significant conversion error for cell 1, and the error of
cell 1 caused by the RC filter differs from errors of cell 2
to cell 12.
OPEN CONNECTION DETECTION
When a cell input (C pin) is open, it affects two cell mea-
surements. Figure 10 shows an open connection to C3,
in an application without external filtering between the C
pins and the cells. During normal ADC conversions (that
is, using the STCVAD command), the LTC6803 will give
near zero readings for B3 and B4 when C3 is open. The
zero reading for B3 occurs because during the measure-
ment of B3, the ADC input resistance will pull C3 to the
C2 potential. Similarly, during the measurement of B4, the
ADC input resistance pulls C3 to the C4 potential.
Figure 11 shows an open connection at the same point in
the cell stack as Figure 10, but this time there is an external
filtering network still connected to C3. Depending on the
value of the capacitor remaining on C3, a normal measure-
ment of B3 and B4 may not give near-zero readings, since
the C3 pin is not truly open. In fact, with a large external
capacitance on C3, the C3 voltage will be charged midway
Figure 9. Adding RC Filtering to the Cell Inputs
(One Cell Connection Shown)
+
100nF
100nF
680313 F09
7.5V
Cn
C(n – 1)
100Ω
100Ω

LTC6803IG-3#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Daisy Chain SPI
Lifecycle:
New from this manufacturer.
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