LTC6803-1/LTC6803-3
16
680313fa
OPERATION
watchdog event, but the CNFGO bit 7 will reflect the state
of this signal. Therefore, the WDTB pin can be used to
monitor external digital events if desired.
SERIAL PORT
Overview
The LTC6803 has an SPI bus compatible serial port. Several
devices can be daisy chained in series. There are two sets
of serial port pins, designated as low side and high side.
The low side and high side ports enable devices to be
daisy chained even when they operate at different power
supply potentials. In a typical configuration, the positive
power supply of the first, bottom device is connected
to the negative power supply of the second, top device,
as shown in Figure 1. When devices are stacked in this
manner, they can be daisy chained by connecting the high
side port of the bottom device to the low side port of the
top device. With this arrangement, the master writes to
or reads from the cascaded devices as if they formed one
long shift register. The LTC6803-1/LTC6803-3 translate the
voltage level of the signals between the low side and high
side ports to pass data up and down the battery stack.
Physical Layer
On the LTC6803-1/LTC6803-3, seven pins comprise the
low side and high side ports. The low side pins are CSBI,
SCKI, SDI and SDO. The high side pins are CSBO, SCKO
and SDOI. CSBI and SCKI are always inputs, driven by the
master or by the next lower device in a stack. CSBO and
SCKO are always outputs that can drive the next higher
device in a stack. SDI is a data input when writing to a
stack of devices. For devices not at the bottom of a stack,
SDI is a data output when reading from the stack. SDOI
is a data output when writing to and a data input when
reading from a stack of devices. SDO is an open-drain
output that is only used on the bottom device of a stack,
where it may be tied with SDI, if desired, to form a single,
bi-directional port. The SDO pin on the bottom device of
a stack requires a pull-up resistor. For devices up in the
stack, SDO should be tied to the local V
or left floating.
To communicate between daisy-chained devices, the high
side port pins of a lower device (CSBO, SCKO and SDOI)
should be connected through high voltage diodes to the
respective low side port pins of the next higher device
(CSBI, SCKI and SDI). In this configuration, the devices
communicate using current rather than voltage. To signal
a logic high from the lower device to the higher device,
the lower device sinks a smaller current from the higher
device pin. To signal a logic low, the lower device sinks
a larger current. Likewise, to signal a logic high from
the higher device to the lower device, the higher device
sources a larger current to the lower device pin. To signal
a logic low, the higher device sources a smaller current.
See Figure 2. Since CSBO, SCKO and SDOI voltages are
close to the V
of high side device, the V
of the high side
device must be at least 5V higher than that of the low side
device to guarantee current flows of the current mode
interface. It is recommended that high voltage diodes be
placed in series with the SPI daisy-chain signals as shown
if Figure 1. These diodes prevent reverse voltage stress
on the IC if a battery group bus bar is removed. See Bat-
tery Interconnection Integrity for additional information.
Standby current consumed in the current mode serial in-
terface is minimized when CSBI, SCKI and SDI are all high.
The voltage mode pin (V
MODE
) determines whether the low
side serial port is configured as voltage mode or current
mode. For the bottom device in a daisy-chain stack, this
pin must be pulled high (tied to V
REG
). The other devices
in the daisy chain must have this pin pulled low (tied to V
)
to designate current mode communication. To designate
the top-of-stack device for polling commands, the TOS
Figure 2. Current Mode Interface
+
WRITE
READ 1
V
SENSE
(WRITE)
+
V
SENSE
(READ)
680313 F02
HIGH SIDE PORT
ON LOWER DEVICE
LOW SIDE PORT
ON HIGHER DEVICE
LTC6803-1/LTC6803-3
17
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OPERATION
Figure 3. Transmission Format (Write)
Figure 4. Transmission Format (Read)
pin on the top device of a daisy chain must be tied high.
The other devices in the stack must have TOS tied low.
See Figure 1.
Data Link Layer
Clock Phase And Polarity: The LTC6803 SPI compatible
interface is configured to operate in a system using CPHA
= 1 and CPOL = 1. Consequently, data on SDI must be
stable during the rising edge of SCKI.
Data Transfers: Every byte consists of 8 bits. Bytes are
transferred with the most significant bit (MSB) first. On a
write, the data value on SDI is latched into the device on
the rising edge of SCKI (Figure 3). Similarly, on a read, the
data value output on SDO is valid during the rising edge of
SCKI and transitions on the falling edge of SCKI (Figure 4).
CSBI must remain low for the entire duration of a com-
mand sequence, including between a command byte and
subsequent data. On a write command, data is latched in
on the rising edge of CSBI.
Network Layer
PEC Byte: The packet error code (PEC) byte is a cyclic
redundancy check (CRC) value calculated for all of the
bits in a register group in the order they are passed, using
the initial PEC value of 01000001 (0x41) and the following
characteristic polynomial:
x
8
+ x
2
+ x + 1
To calculate the 8-bit PEC value, a simple procedure can
be established:
1. Initialize the PEC to 0100 0001.
2. For each bit DIN coming into the register group, set
IN0 = DIN XOR PEC[7], then IN1=PEC[0] XOR IN0,
IN2 = PEC[1] XOR IN0.
3. Update the 8-bit PEC as PEC[7] = PEC[6],
PEC[6] = PEC[5],……PEC[3] = PEC[2], PEC[2] = IN2,
PEC[1] = IN1, PEC[0] = IN0.
4. Go back to step 2 until all data are shifted. The 8-bit
result is the final PEC byte.
SDI MSB (CMD) BIT 6 (CMD) LSB (PEC) MSB (DATA) LSB (PEC)
680313 F03
SCKI
CSBI
SDI
SDO
MSB (CMD) BIT 6 (CMD) LSB (PEC)
MSB (DATA) LSB (PEC)
680313 F04
SCKI
CSBI
LTC6803-1/LTC6803-3
18
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OPERATION
An example to calculate the PEC is listed in Table 1 and
Figure 5. The PEC of the 1 byte data 0x01 is computed as
0xC7 after the last bit of the byte clocked in. For multiple
byte data, the PEC is valid at the end (LSB) of the last byte.
LTC6803 calculates PEC byte for any command or data
received and compares it with the PEC byte following the
command or data. The command or data is regarded as
valid only if the PEC bytes match. LTC6803 also attaches
the calculated PEC byte at the end of the data it shifts out.
For daisy-chained LTC6803-1/LTC6803-3, each device
computes the PEC byte based on the data it sends out
or receives for itself. The data passing through for other
devices do affect its PEC. On a read command, each device
shifts its data out with, and then shifts out the PEC byte it
computed, MSB first. For example, when reading the flag
registers from two stacked devices (bottom device A and
top device B), the data will be output in the following order:
FLGR0(A), FLGR1(A), FLGR2(A), PEC(A), FLGR0(B),
FLGR1(B), FLGR2(B), PEC(B )
On a write command, each device receives its data and
then the PEC byte, MSB first. For example, when writing
configuration registers to two stacked devices (bottom
device A and top device B), the data will be input in the
following order:
CFGRR0(B), CFGR1(B),……, CFGR5(B), PEC(B),
CFGR0(A), CFGR1(A),……, CFGR5(A), PEC(A)
Broadcast Commands: A broadcast command is one to
which all devices on the bus will respond, regardless of
device address. See the Bus Protocols and Commands
sections.
In daisy-chained configurations, all devices in the chain
receive the command bytes simultaneously. For example,
to initiate ADC conversions in a stack of devices, a single
STCVAD command is sent, and all devices will start con-
versions at the same time. For read and write commands,
a single command is sent, and then the stacked devices
effectively turn into a cascaded shift register, in which
data is shifted through each device to the next higher (on
a write) or the next lower (on a read) device in the stack.
See the Serial Command Examples section.
Polling Methods: For ADC conversions, three methods can
be used to determine ADC completion. First, a controller
can start an ADC conversion and wait for the specified
conversion time to pass before reading the results. The
second method is to hold CSBI low after an ADC start
command has been sent. The ADC conversion status will
be output on SDO (Figure 6). A problem with the second
method is that the controller is not free to do other serial
communication while waiting for ADC conversions to
complete. The third method overcomes this limitation.
The controller can send an ADC start command, perform
other tasks, and then send a poll ADC converter status
(PLADC) command to determine the status of the ADC
conversions (Figure 7). For OV/UV interrupt status, the poll
interrupt status (PLINT) command can be used to quickly
determine whether any cell in a stack is in an overvoltage
or undervoltage condition (Figure 7).
Table 1. Procedure to Calculate PEC Byte
CLOCK
CYCLE DIN IN0 IN1 IN2 PEC[7] PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[0]
0 0 0 1 0 0 1 0 0 0 0 0 1
1 0 1 1 0 1 0 0 0 0 0 1 0
2 0 0 1 1 0 0 0 0 0 0 1 1
3 0 0 0 1 0 0 0 0 0 1 1 0
4 0 0 0 0 0 0 0 0 1 1 0 0
5 0 0 0 0 0 0 0 1 1 0 0 0
6 0 0 0 0 0 0 1 1 0 0 0 0
7 1 1 1 1 0 1 1 0 0 0 0 0
8 1 1 0 0 0 1 1 1

LTC6803IG-3#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Daisy Chain SPI
Lifecycle:
New from this manufacturer.
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