LTC6803-1/LTC6803-3
7
680313fa
TYPICAL PERFORMANCE CHARACTERISTICS
Internal Die Temperature
Measurement Error Using an
8mV/°K Scale Factor
External Temperature
Measurement Total Unadjusted
Error vs Input
ADC INL ADC DNL
Cell Input Bias Current During
Standby and Hardware Shutdown
ADC Normal Mode Rejection
vs Frequency
0
–10
–30
–50
–20
–40
–60
–70
FREQUENCY (Hz)
REJECTION (dB)
680313 G13
10 10k 100k1k100
INPUT (V)
0
INL (BITS)
2.0
1.5
0.5
1.0
0
–1.0
–0.5
–1.5
–2.0
1 2 4
680313 G14
53
INPUT (V)
0
DNL (BITS)
1.0
0.8
0.2
0.4
0.6
0
–0.6
–0.4
–0.2
–0.8
–1.0
1 2 4
680313 G15
53
Standby Supply Current
vs Supply Voltage
Supply Current vs Supply Voltage
During Continuous Conversions
TEMPERATURE (°C)
–40
0
CELL INPUT BIAS CURRENT (nA)
5
15
20
25
50
35
0
40
60
680313 G16
10
40
45
30
–20 20
80
100
120
C12
C6
C1
CELL INPUT = 3.6V
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (µA)
6
8
10
30
50
680313 G17
4
2
0
10 20 40
12
14
16
60
125°C
85°C
25°C
–40°C
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (µA)
650
700
30
50
680313 G18
600
10 20 40
750
800
850
60
125°C
85°C
25°C
–40°C
CDC = 2
CONTINUOUS CONVERSION
TEMPERATURE INPUT VOLTAGE (V)
–4.5
TOTAL UNADJUSTED ERROR (mV)
–1.5
1.5
4.5
–3.0
0
3.0
1.0 2.0 3.0 4.0
680313 G20
5.00.50 1.5 2.5 3.5 4.5
T
A
= 125°C
T
A
= 85°C
T
A
= 25°C
T
A
= –40°C
TEMPERATURE (°C)
0
–10
E = (AMBIENT TEMP-INTERNAL
DIE TEMP READING) (°C)
–5
0
5
10
15
25
50 75 100
680313 G19
125 150
10 SAMPLES
LTC6803-1/LTC6803-3
8
680313fa
TYPICAL PERFORMANCE CHARACTERISTICS
V
REF
Line Regulation
V
REG
Load Regulation
V
REF
Load Regulation
SOURCING CURRENT (µA)
0
V
REF
(V)
3.09
3.08
3.07
3.06
3.04
3.05
10 100
680313 G22
1000
T
A
= 85°C
T
A
= –40°C
T
A
= 25°C
SUPPLY VOLTAGE (V)
0
V
REF
(V)
3.074
3.072
3.070
3.068
3.066
3.064
3.062
3.060
20 4010 30 50
680313 G23
60
T
A
= 85°C
T
A
= –40°C
T
A
= 25°C
NO EXTERNAL LOAD ON V
REF
, CDC = 2
(CONTINUOUS CELL CONVERSIONS)
SUPPLY CURRENT (mA)
0
4.0
V
REG
(V)
4.2
4.4
4.6
4.8
5.2
2
4 6 8
680313 G24
10 12
5.0
T
A
= 125°C
T
A
= 85°C
T
A
= 25°C
T
A
= –40°C
V
+
= 43.2V
V
REF
Output Voltage
vs Temperature
TEMPERATURE (°C)
–50
V
REF
(V)
3.070
3.068
3.064
3.060
3.066
3.062
3.058
3.056
500 100
680313 G21
12525–25 75
5 REPRESENTATIVE UNITS
V
REG
Line Regulation
Internal Discharge Resistance
vs Cell Voltage
SUPPLY VOLTAGE (V)
0
4.0
V
REG
(V)
4.5
5.0
5.5
10 20 30 40
680313 G25
50
60
T
A
= 125°C
T
A
= 85°C
T
A
= 25°C
T
A
= –40°C
CDC = 2
CONTINUOUS CONVERSIONS
Die Temperature Increase vs
Discharge Current in Internal FET
DISCHARGE CURRENT PER CELL (mA)
0
INCREASE IN DIE TEMPERATURE (°C)
50
5
45
35
25
15
40
30
20
10
0
40 8020 60
680313 G27
30 7010 50
1 CELL
DISCHARGING
6 CELLS
DISCHARGING
12 CELLS
DISCHARGING
ALL 12 CELLS AT 3.6V
V
S
= 43.2V
T
A
= 25°C
Cell Conversion Time
TEMPERATURE (°C)
–40
CONVERSION TIME (ms)
13.20
13.15
13.10
13.05
13.00
12.80
12.85
12.90
12.95
20–20 400 80 10060
680313 G28
120
CELL VOLTAGE (V)
0
DISCHARGE RESISTANCE (Ω)
50
5
45
35
25
15
40
30
20
10
0
2.5 4.51.5 3.5
680313 G26
5.02.0 4.01.0 3.00.5
T
A
= 105°C
T
A
= 85°C
T
A
= 25°C
T
A
= –45°C
LTC6803-1/LTC6803-3
9
680313fa
PIN FUNCTIONS
To ensure pin compatibility with the LTC6802-1, the
LTC6803-1 is configured such that the bottom cell input
(C0) is connected internally to the negative supply voltage
(V
). The LTC6803-3 offers a unique pinout with an input
for the bottom cell (C0). This simple functional difference
offers the possibility for enhanced cell 1 measurement
accuracy, enhanced SPI noise tolerance and simplified
wiring. More information is provided in the applications
section entitled Advantages of Kelvin Connections for C0.
CSBO (Pin 1): Chip Select Output (Active Low). CSBO is
a buffered version of the chip select input, CSBI. CSBO
drives the next IC in the daisy chain. See Serial Port in the
Applications Information section.
SDOI (Pin 2): Serial Data I/O Pin. SDOI transfers data to
and from the next IC in the daisy chain. See Serial Port in
the Applications Information section.
SCKO (Pin 3): Serial Clock Output. SCKO is a buffered ver-
sion of SCKI. SCKO drives the next IC in the daisy chain.
See Serial Port in the Applications Information section.
V
+
(Pin 4): Positive Power Supply. Pin 4 can be tied to the
most positive potential in the battery stack or an isolated
power supply. V
+
must be greater than the most positive
potential in the battery stack under normal operation. With
an isolated power supply, LTC6803 can be turned off by
simply shutting down V
+
.
C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins
5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27): C1 through
C12 are the inputs for monitoring battery cell voltages. The
negative terminal of the bottom cell is tied to pin V
for
LTC6803-1, pin C0 for LTC6803-3 . The next lowest potential
is tied to C1 and so forth. See the figures in the Applica-
tions Information section for more details on connecting
batteries to the LTC6803-1 and LTC6803-3. The LTC6803
can monitor a series connection of up to 12 cells. Each
cell in a series connection must have a common mode
voltage that is greater than or equal to the cells below it.
100mV negative voltages are permitted.
S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins
6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28): S1 though
S12 pins are used to balance battery cells. If one cell in a
series becomes overcharged, an S output can be used to
discharge the cell. Each S output has an internal N-channel
MOSFET for discharging. See the Block Diagram. The
NMOS has a maximum on resistance of 20Ω. An external
resistor should be connected in series with the NMOS to
dissipate heat outside of the LTC6803 package. When
using the internal MOSFETs to discharge cells, the die
temperature should be monitored. See Power Dissipation
and Thermal Shutdown in the Applications Information
section. The S pins also feature an internal pull-up PMOS.
This allows the S pins to be used to drive the gates of
external MOSFETs for higher discharge capability.
C0 (Pin 29 on LTC6803-3): Negative Terminal of the Bot-
tom Battery Cell. C0 and V
form Kelvin connections to
eliminate effect of voltage drop at the V
trace.
V
(Pin 29 on LTC6803-1/ Pin 30 on LTC6803-3): Connect
V
to the most negative potential in the series of cells.
NC (Pin 30 on LTC6803-1/Pin 31 on LTC6803-3 ): This pin
is not used and is internally connected to V
through 10Ω.
It can be left unconnected or connected to V
on the PCB.
V
TEMP1
, V
TEMP2
(Pins 31, 32 on LTC6803-1/ Pins 32, 33
on LTC6803-3 ): Temperature Sensor Inputs. The ADC
measures the voltage on V
TEMPn
with respect to V
and
stores the result in the TMP registers. The ADC measure-
ments are relative to the V
REF
pin voltage. Therefore a
simple thermistor and resistor combination connected
to the V
REF
pin can be used to monitor temperature. The
V
TEMP
inputs can also be general purpose ADC inputs.
Any voltage from 0V to 5.125V referenced to V
can be
measured.
V
REF
(Pin 33 on LTC6803-1/ Pin 34 on LTC6803-3 ): 3.065V
Voltage Reference Output. This pin should be bypassed
with a 1µF capacitor. The V
REF
pin can drive a 100k resis-
tive load connected to V
. Larger loads should be buffered
with an LT6003 op amp, or similar device.

LTC6803IG-3#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Daisy Chain SPI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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