LTC6803-1/LTC6803-3
13
680313fa
OPERATION
Figure 1. 96-Cell Battery Stack, Daisy-Chain Interface. This is a Simplified Schematic Showing the Basic Multi-IC Architecture
+
+
+
+
+
+
+
+
+
+
+
+
CSBO
SDOI
SCKO
V
+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
CSBI
SDO
SDI
SCKI
V
MODE
GPIO2
GPIO1
WDTB
TOS
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
C0
S1
C1
S2
C2
S3
C3
LTC6803-3
IC #8
BATTERIES #25 TO #84
AND
LTC6803-3 ICs #3 TO #7
BATTERY
POSITIVE
350V
+
+
+
+
+
+
+
+
+
+
+
+
CSBO
SDOI
SCKO
V
+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
CSBI
SDO
SDI
SCKI
V
MODE
GPIO2
GPIO1
WDTB
TOS
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
C0
S1
C1
S2
C2
S3
C3
LTC6803-3
IC #1
+
+
+
+
+
+
+
+
+
+
+
+
CSBO
SDOI
SCKO
V
+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
CSBI
SDO
SDI
SCKI
V
MODE
GPIO2
GPIO1
WDTB
TOS
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
C0
S1
C1
S2
C2
S3
C3
LTC6803-3
IC #2
V2
V2
+
V2
3V
680313 F01
3V
OE2
DIGITAL
ISOLATOR
V1
V1
V1
+
OE1
MPU
MODULE
IO
CS
MISO
MISI
CLK
LTC6803-1/LTC6803-3
14
680313fa
OPERATION
when V
+
= 44V. All circuits are turned off except the serial
interface and the voltage regulator. For the lowest possible
standby current consumption all SPI logic inputs should
be set to logic 1 level. The LTC6803 can be programmed
for standby mode by setting the comparator duty cycle
configuration bits, CDC[2:0], to 0. If the part is put into
standby mode while ADC measurements are in progress,
the measurements will be interrupted and the cell voltage
registers will be in an indeterminate state. To exit standby
mode, the CDC bits must be written to a value other than 0.
MEASURE MODE
The LTC6803 is in measure mode when the CDC bits are
programmed with a value from 1 to 7. When CDC = 1 the
LTC6803 is on and waiting for a start ADC conversion
command. When CDC is 2 through 7 the IC monitors each
cell voltage and produces an interrupt signal on the SDO
pin indicating all cell voltages are within the UV and OV
limits. The value of the CDC bits determines how often
the cells are monitored, and how much average supply
current is consumed.
There are two methods for indicating the UV/OV inter-
rupt status: toggle polling (using a 1kHz output signal)
and level polling (using a high or low output signal). The
polling methods are described in the Serial Port section.
The UV/OV limits are set by the V
UV
and V
OV
values in the
configuration registers. When a cell voltage exceeds the
UV/OV limits a bit is set in the flag register. The UV and
OV flag status for each cell can be determined using the
Read Flag Register Group.
An ADC measurement can be requested at any time when
the IC is in measure mode. To initiate cell voltage measure-
ments while in measure mode, a Start A/D Conversion is
sent. After the command has been sent, the LTC6803 will
indicate the A/D converter status via toggle polling or level
polling (as described in the Serial Port section). During
cell voltage measurement commands, the UV and OV flags
(within the flag register group) are also updated. When
the measurements are complete, the part will continue
monitoring UV and OV conditions at the rate designated
by the CDC bits. Note that there is a 5µs window during
each UV/OV comparison cycle where an ADC measure-
ment request may be missed. This is an unlikely event.
For example, the comparison cycle is 2 seconds when
CDC = 7. Use the CLEAR command to detect missing
ADC commands.
Operating with Less than 12 Cells
If fewer than 12 cells are connected to the LTC6803, the
unused input channels must be masked. The MCxI bits in
the configuration registers are used to mask channels. In
addition, the LTC6803 can be configured to automatically
bypass the measurements of the top 2 cells, reducing power
consumption and measurement time. If the CELL10 bit is
high, the inputs for cell 11 and cell 12 are masked and only
the bottom 10 cell voltages will be measured. By default,
the CELL10 bit is low, enabling measurement of all 12 cell
voltages. Additional information regarding operation with
less than 12 cells is provided in the applications section.
ADC RANGE AND OUTPUT FORMAT
The ADC outputs a 12-bit code with an offset of 0x200
(512 decimal). The input voltage can be calculated as:
V
IN
= (D
OUT
– 512) • V
LSB
; V
LSB
= 1.5mV
where D
OUT
is a decimal integer.
For example, a 0V input will have an output reading
of 0x200. An ADC reading of 0x000 means the input
was –0.768V. The absolute ADC measurement range is
–0.768V to 5.376V. The resolution is V
LSB
= 1.5mV = (5.376
+ 0.768)/2
12
.
The useful range is –0.3V to 5V. This range
allows monitoring super capacitors, which could have small
negative voltage. Inputs below –0.3V exceed the absolute
maximum rating of the C pins. If all inputs are negative
then the ADC range is reduced to –0.1V. Inputs above 5V
will have noisy ADC readings (see Typical Performance
Characteristics curves).
ADC MEASUREMENTS DURING CELL BALANCING
The primary cell voltage ADC measurement commands
(STCVAD and STOWAD) automatically turn off a cell’s
discharge switch while its voltage is being measured. The
discharge switches for the cell above and the cell below will
also be turned off during the measurement. For example,
discharge switches S4, S5 and S6 will be off while cell 5
is being measured. The UV/OV comparison conversions in
LTC6803-1/LTC6803-3
15
680313fa
OPERATION
CDC modes 2 through 7 also cause a momentary turn-off
of the discharge switch. For example, switches S4, S5 and
S6 will be off while cell 5 is checked for a UV/OV condition.
In some systems it may be desirable to allow discharging to
continue during cell voltage measurements. The cell voltage
ADC conversion commands STCVDC and STOWDC allow
the discharge switches to remain on during cell voltage
measurements. This feature allows the system to perform
a self test to verify the discharge functionality.
ADC REGISTER CLEAR COMMAND
The clear command can be used to clear the cell voltage
registers and temperature registers. The clear command
will set all registers to 0xFFF. This command is used to
make sure conversions are being made. When cell volt-
ages are stable, ADC results could stay the same. If a start
ADC conversion command is sent to the LTC6803 but the
PEC fails to match then the command is ignored and the
voltage register contents also will not change. Sending a
clear command then reading back register contents is a
way to make sure LTC6803 is accepting commands and
performing new measurements. The clear command takes
1ms to execute.
ADC CONVERTER SELF TEST
Two self-test commands can be used to verify the func-
tionality of the digital portions of the ADC. The self tests
also verify the cell voltage registers and temperature
monitoring registers. During these self tests a test signal
is applied to the ADC. If the circuitry is working properly all
cell voltage and temperature registers will contain 0x555
or 0xAAA. The time required for the self-test function is
the same as required to measure all cell voltages or all
temperature sensors.
MULTIPLEXER AND REFERENCE SELF TEST
The LTC6803 uses a multiplexer to measure the 12 bat-
tery cell inputs, as well as the temperature signals. A
diagnostic command is used to validate the function of
the multiplexer, the temperature sensor, and the precision
reference circuit. Diagnostic registers will be updated after
each diagnostic test. The muxfail bit of the registers will
be 1 if the multiplexer self test fails.
A constant voltage generated by the 2nd reference circuit
will be measured by the ADC and the results written to the
diagnostic register. The voltage reading should be 2.5V
±16%. Readings outside this range indicate a failure of the
temperature sensor circuit, the precision reference circuit,
or the analog portion of the ADC. The DAGN command
executes in 16.4ms, which is the sum of the 12-cell t
CYCLE
and 3 temperature t
CYCLE
. The diagnostic read command
can be used to read the registers.
USING THE GENERAL PURPOSE INPUTS/OUTPUTS
(GPIO1, GPIO2)
The LTC6803 has two general purpose digital input/output
pins. By writing a GPIO configuration register bit to a logic
low, the open-drain output can be activated. The GPIOs
give the user the ability to turn on/off circuitry around
the LTC6803. One example might be a circuit to verify the
operation of the system.
When a GPIO configuration bit is written to a logic high,
the corresponding GPIO pin may be used as an input.
The read back value of that bit will be the logic level that
appears at the GPIO pin.
WATCHDOG TIMER CIRCUIT
The LTC6803 includes a watchdog timer circuit. The
watchdog timer is on for all modes except CDC = 0. The
watchdog timer times out if no valid command is received
for 1 to 2.5 seconds. When the watchdog timer circuit
times out, the WDTB open-drain output is asserted low
and the configuration register bits are reset to their default
(power-up) state. In the power-up state, CDC is 0, the S
outputs are off and the IC is in the low power standby
mode. The WDTB pin remains low until a valid command
is received. The watchdog timer provides a means to turn
off cell discharging should communications to the MPU
be interrupted. There is no need for the watchdog timer
at CDC = 0 since discharging is off. The open-drain WDTB
output can be wire ORd with other external open-drain
signals. Pulling the WDTB signal low will not initiate a

LTC6803IG-3#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Daisy Chain SPI
Lifecycle:
New from this manufacturer.
Delivery:
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