LTC3300-1
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For more information www.linear.com/LTC3300-1
PIN FUNCTIONS
Note: The convention adopted in this data sheet is to refer
to the transformer winding paralleling an individual battery
cell as the primary and the transformer winding paralleling
multiple series-stacked cells as the secondary, regardless
of the direction of energy transfer.
G6S, G5S, G4S, G3S, G2S, G1S (Pins 1, 3, 5, 7, 9,
11): G1S through G6S are gate driver outputs for driving
external NMOS transistors connected in series with the
secondary windings of transformers whose primaries are
connected in parallel with battery cells 1 through 6. For
the minimum part count balancing application employing
a single transformer (CTRL = V
REG
), G2S through G6S
are no connects.
I6S, I5S, I4S, I3S, I2S, I1S (Pins 2, 4, 6, 8, 10, 12): I1S
through I6S are current sense inputs for measuring sec
-
ondary winding current in transformers whose primaries
are connected in parallel with battery cells 1 through 6.
For the minimum part count balancing application employ
-
ing
a single transformer (CTRL = V
REG
), I2S through I6S
should be tied to V
.
RTONS (Pin 13): Secondary Winding Max t
ON
Setting
Resistor. The RTONS pin servos to 1.2V. A resistor to V
programs the maximum on-time for all external NMOS
transistors connected in series with secondary windings.
This protects against a short-circuited current sense re
-
sistor in any secondary winding. To defeat this function,
connect R
TONS to V
REG
. The secondary winding OVP
threshold (see WDT pin) is also slaved to the value of the
R
TONS
resistor.
RTONP (Pin 14): Primary Winding Max t
ON
Setting
Resistor. The RTONP pin servos to 1.2V. A resistor to V
programs the maximum on-time for all external NMOS
transistors connected in series with primary windings.
This protects against a short-circuited current sense
resistor in any primary winding. To defeat this function,
connect RTONP to V
REG
.
CTRL: (Pin 15): Control Input. The CTRL pin configures
the LTC3300-1 for the minimum part count application
employing a single transformer if CTRL is tied to V
REG
or
for the multiple transformer application if CTRL is tied to
V
. This pin must be tied to either V
REG
or V
.
CSBI (Pin 16): Chip Select (Active Low) Input. The CSBI
pin interfaces to a rail-to-rail output logic gate if V
MODE
is tied to V
REG
. CSBI must be driven by the CSBO pin of
another LTC3300-1 if V
MODE
is tied to V
. See Serial Port
in the Applications Information section.
SCKI (Pin 17): Serial Clock Input. The SCKI pin interfaces
to a rail-to-rail output logic gate if V
MODE
is tied to V
REG
.
SCKI must be driven by the SCKO pin of another LTC3300-1
if V
MODE
is tied to V
. See Serial Port in the Applications
Information section.
SDI (Pin 18): Serial Data Input. When writing data to the
LTC3300-1, the SDI pin interfaces to a rail-to-rail output
logic gate if V
MODE
is tied to V
REG
or must be driven by
the SDOI pin of another LTC3300-1 if V
MODE
is tied to V
.
See Serial Port in the Applications Information section.
SDO (Pin 19): Serial Data Output. When reading data
from the LTC3300-1, the SDO pin is an NMOS open-drain
output if V
MODE
is tied to V
REG
. The SDO pin is not used
if V
MODE
is tied to V
. See Serial Port in the Applications
Information section.
WDT (Pin 20): Watchdog Timer Output (Active High). At
initial power-up and when not attempting to execute a valid
balance command, the WDT pin is high impedance and will
be pulled high (internally clamped to ~5.6V) if an external
pull-up resistor is present. While balancing (or attempt
-
ing to balance but not able to due to voltage/temperature
faults) and during normal communication activity, the WDT
pin is pulled low by a precision current source slaved to
the R
TONS
resistor. However, if no valid command byte is
written for 1.5 seconds (typical), the WDT output will go
back high. When WDT is high, all balancers are off. The
watchdog timer function can be disabled by connecting
WDT to V
. The secondary winding OVP function can also
be implemented using this pin (See Operation section).
V
(Pin 21): Connect V
to the most negative potential in
the series of cells.
I1P, I2P, I3P, I4P, I5P, I6P (Pins 22, 25, 28, 31, 34, 37):
I1P through I6P are current sense inputs for measuring
primary winding current in transformers connected in
parallel with battery cells 1 through 6.
LTC3300-1
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For more information www.linear.com/LTC3300-1
PIN FUNCTIONS
G1P, G2P, G3P, G4P, G5P, G6P (Pins 23, 26, 29, 32, 35,
38): G1P through G6P are gate driver outputs for driving
external NMOS transistors connected in series with the
primary windings of transformers connected in parallel
with battery cells 1 through 6.
C1, C2, C3, C4, C5, C6 (Pins 24, 27, 30, 33, 36, 39):
C1 through C6 connect to the positive terminals of bat
-
tery cells 1 through 6. Connect the negative terminal of
battery cell 1 to V
.
BOOST
+
(Pin 40): Boost
+
Pin. Connects to the anode of
the external flying capacitor used for generating sufficient
gate drive necessary for balancing the topmost battery cell
in a given LTC3300-1 sub-stack. A Schottky diode from C6
to BOOST
+
is needed as well. Alternately, the BOOST
+
pin
can connect to one cell up in the above sub-stack (if pres-
ent). This pin is effectively C7. (Note: “Sub-stack” refers
to the 3-6 batter
y cells connected locally to an individual
L
TC3300-1 as part of a larger stack.)
BOOST
(Pin 41): Boost
Pin. Connects to the cathode of
the external flying capacitor used for generating sufficient
gate drive necessary for balancing the topmost battery cell
in a given LTC3300-1 sub-stack. Alternately, if the BOOST
+
pin connects to the next higher cell in the above sub-stack
(if present), this pin is a no connect.
BOOST (Pin 42): Enable Boost Pin. Connect BOOST to V
REG
to enable the boosted gate drive needed for balancing the
top cell in a given LTC3300-1 sub-stack. If the BOOST
+
pin
can be connected to the next cell up in the stack (i.e., C1
of the next LTC3300-1 in the stack), then BOOST should
be tied to V
and BOOST
no connected. This pin must
be tied to either V
REG
or V
.
SDOI (Pin 43): Serial Data Output/Input. SDOI transfers
data to and from the next IC higher in the daisy chain when
writing and reading. See Serial Port in the Applications
Information section.
SCKO (Pin 44): Serial Clock Output. SCKO is a buffered
and one-shotted version of the serial clock input, SCKI,
when CSBI is low. SCKO drives the next IC higher in the
daisy chain. See Serial Port in the Applications Informa
-
tion section.
CSBO (Pin 45): Chip Select (Active Low) Output. CSBO
is
a buffered version of the chip select input, CSBI. CSBO
drives the next IC higher in the daisy chain. See Serial Port
in the Applications Information section.
V
MODE
(Pin 46): Voltage Mode Input. When V
MODE
is tied
to V
REG
, the CSBI, SCKI, SDI and SDO pins are configured
as voltage inputs and outputs. This means these pins
accept V
REG
-referred rail-to-rail logic levels. Connect
V
MODE
to V
REG
when the LTC3300-1 is the bottom device
in a daisy chain.
When V
MODE
is tied to V
, the CSBI, SCKI and SDI pins
are configured as current inputs and outputs, and SDO is
unused. Connect V
MODE
to V
when the LTC3300-1 is be-
ing driven by another LTC3300-1 lower in the daisy chain.
This pin must be tied to either V
REG
or V
.
TOS (Pin 47): Top Of Stack Input. Tie TOS to V
REG
when
the LTC3300-1 is the top device in a daisy chain. Tie TOS
to V
when the LTC3300-1 is any other device in the daisy
chain. When TOS is tied to V
REG
, the LTC3300-1 ignores
the SDOI input. When TOS is tied to V
, the LTC3300-1
expects data to be passed to and from the SDOI pin. This
pin must be tied to either V
REG
or V
.
V
REG
(Pin 48): Linear Voltage Regulator Output. This 4.8V
output should be bypassed with a 1µF or larger capacitor
to V
. The V
REG
pin is capable of supplying up to 40mA
to internal and external loads. The V
REG
pin does not sink
current.
V
(Exposed Pad Pin 49): The exposed pad should be
connected to a continuous (ground) plane biased at V
on
the second layer of the printed circuit board by several
vias directly under the LTC3300-1.
LTC3300-1
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For more information www.linear.com/LTC3300-1
BLOCK DIAGRAM
+
+
BOOST
+
BOOST
GATE DRIVE
GENERATOR
6-CELL
SYNCHRONOUS
FLYBACK
CONTROLLER
BALANCER
C6
C6
C5
DATA
12
STATUS
12
C5
50mV/0
0/50mV
V
REG
V
+
39
BOOST
BOOST
V
REG
SD
C6
40mA
MAX
V
POR
4.8V
42
41
G6P
38
I6P
37
I6S
2
G6S
PINS 3 TO 10,
25 TO 36
1
BALANCER
CONTROLLER
+
C2
C1
V
50mV/0
0/50mV
V
REG
V
+
24
G1P
23
I1P
22
I1S
12
G1S
11
20
BALANCER
CONTROLLER
2
ACTIVE
2
MAX ON-TIME
VOLT-SEC
CLAMPS
THERMAL
SHUTDOWN
BOOST
+
40
V
RTONS
13
CTRL
15
V
WDT
16
CSBI
17
SCKI
18
SDI
19
SDO
43
SDOI
44
SCKO
45
CSBO
RESET
RTONP
33001 BD
14
TOS
47
V
5.6V
1.2V
R
TONS
V
21
EXPOSED
PAD
49
V
MODE
46
LEVEL-SHIFTING
SERIAL
INTERFACE
V
REG
48
VOLTAGE
REGULATOR
CRC/RCRC
PACKET ERROR
CHECKING
16
WATCHDOG
TIMER

LTC3300IUK-1#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Hi Eff Bi-dir Multicell Bat Balancer
Lifecycle:
New from this manufacturer.
Delivery:
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