LTC3300-1
40
33001fb
For more information www.linear.com/LTC3300-1
Figure 18. Typical Pin Voltages for Six 4.2V Cells
LTC3300-1
(EXPOSED PAD = 0V)
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
0V TO 4.8V
0V
21V
16.8V TO 25.2V
16.8V
16.8V
12.6V TO 21V
12.6V
12.6V
8.4V TO 16.8V
8.4V
8.4V
4.2V TO 12.6V
4.2V
G6S—PIN 1
I6S
G5S
I5S
G4S
I4S
G3S
I3S
G2S
I2S
G1S
I1S
C5
G5P
I5P
C4
G4P
I4P
C3
G3P
I3P
C2
G2P
I2P
V
REG
TOS
V
MODE
CSBO
SCKO
SDOI
BOOST
BOOST
–
BOOST
+
C6
G6P
I6P
1.2V
1.2V
0V/4.8V
0V TO 4.8V
0V TO 4.8V
0V TO 4.8V
0V TO 4.8V
0V TO 4.8V
0V
0V
0V TO 8.4V
4.2V
RTONS
RTONP
CTRL
CSBI
SCKI
SDI
SDO
WDT
V
–
I1P
G1P
C1
4.8V
0V/4.8V
0V/4.8V
24.5V
24.5V
24.5V
0V/4.8V
21V TO 25.2V
25.2V TO 29.4V
25.2V
21V TO 29.4V
21V
33001 F18
APPLICATIONS INFORMATION
PCB Layout Considerations
The LTC3300-1 is capable of operation with as much as
40V between BOOST
+
and V
–
. Care should be taken on
the PCB layout to maintain physical separation of traces
at different potentials. The pinout of the LTC3300-1 was
chosen to facilitate this physical separation. There is no
more than 8.4V between any two adjacent pins with the
exception of two instances (V
MODE
to CSBO, BOOST to
SDOI/BOOST
–
). In both instances, one of the pins (V
MODE
,
BOOST) is pin-strapped in the application to V
–
or V
REG
and does not need to route far from the LTC3300-1. The
package body is used to separate the highest voltage
(e.g., 25.2V) from the lowest voltage (0V). As an example,
Figure18 shows the DC voltage on each pin with respect
to V
–
when six 4.2V battery cells are connected to the
LTC3300-1.
2. The differential cell inputs (C6 to C5, C5 to C4, …, C1 to
exposed pad) should be bypassed with a 1µF or larger
capacitor as close to the LTC3300-1 as possible. This
is in addition to bulk capacitance present in the power
stages.
3. Pin 21 (V
–
) is the ground sense for current sense resis-
tors connected to I1S-I6S and I1P (seven resistors).
Pin 21 should be Kelvined as well as possible with low
impedance traces to the ground side of these resistors
before connecting to the L
TC3300-1 exposed pad.
4. Cell inputs C1 to C5 are the ground sense for current
sense resistors connected to I2P-I6P (five resistors).
These pins should be Kelvined as well as possible
with low impedance traces to the ground side of these
resistors.
5. The ground side of the maximum on-time setting resis
-
tors connected to the RTONS and RTONP pins should
be Kelvined to Pin 21 (V
–
) before connecting to the
LTC3300-1 exposed pad.
6. Trace lengths from the LTC3300-1 gate drive outputs
(G1S-G6S and G1P-G6P) and current sense inputs
(I1S-I6S and I1P-I6P) should be as short as possible.
7. The boosted gate drive components (diode and ca
-
pacitor), if used, should form a tight loop close to the
LTC3300-1 C6, BOOST
+
, and BOOST
–
pins.
8. For the external power components (transformer, FETs
and current sense resistors), it is important to keep the
area encircled by the two high speed current switching
loops (primary and secondary) as tight as possible.
This is greatly aided by having two additional bypass
capacitors local to the power circuit: one differential
cell to cell and one from the transformer secondary to
local V
–
.
A representative layout incorporating all of these recom-
mendations is implemented on the DC2064A demo board
for the L
TC3300-1 (with further explanation in its accom-
panying
demo board manual). PCB layout files (.GRB) are
also available from the factor
y
.
Additional “good practice” layout considerations are as
follows:
1. The V
REG
pin should be bypassed to the exposed pad
and to V
–
, each with 1µF or larger capacitors as close
to the LTC3300-1 as possible.
