LTC3300-1
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Table 9. LTC3300-1 Failure Mechanism Effect Analysis
SCENARIO EFFECT DESIGN MITIGATION
Top cell (C6) input connection loss to LTC3300-1. Power will come from highest connected cell
input or via data port fault current.
Clamp diodes at each pin to C6 and V
–
(within IC)
provide alternate power path. Diode conduction at
data ports will impair communication with higher
potential units.
Bottom cell (V
–
) input connection loss to
LTC3300-1.
Power will come from lowest connected cell
input or via data port fault current.
Clamp diodes at each pin to C6 and V
–
(within IC)
provide alternate power path. Diode conduction at
data ports will impair communication with higher
potential units.
Random cell (C1-C5) input connection loss to
LTC3300-1.
Power-up sequence at IC inputs/differential
input voltage overstress.
Clamp diodes at each pin to C6 and V
–
(within IC)
provide alternate power path. Zener diodes across
each cell voltage input pair (within IC) limit stress.
Disconnection of a harness between a sub-stack
of battery cells and the LTC3300-1 (in a system of
stacked groups).
Loss of all supply connections to the IC. Clamp diodes at each pin to C6 and V
–
(within
IC) provide alternate power path if there are other
devices (which can supply power) connected to
the LTC3300-1. Diode conduction at data ports
will impair communication with higher potential
units.
Secondary winding connection loss to battery
stack.
Secondary winding power FET could be
subjected to a higher voltage as bypass
capacitor charges up.
WDT pin implements a secondary winding OVP
circuit which will detect overvoltage and terminate
balancing.
Shorted primary winding sense resistor. Primary winding peak current cannot be
detected to shut off primary switch.
Maximum ON-time set by R
TONP
resistor will shut
off primary switch if peak current detect doesn’t
occur.
Shorted secondary winding sense resistor. Secondary winding peak current cannot be
detected to shut off secondary switch.
Maximum ON-time set by R
TONS
resistor will
shut off secondary switch if peak current detect
doesn’t occur.
Data link disconnection between stacked LTC3300-1
units.
Break of daisy-chain communication (no stress
to ICs). Communication will be lost to devices
above the disconnection. The devices below the
disconnection are still able to communicate and
perform all functions.
If the watchdog timer is enabled, all balancers
above the fault will be turned off after 1.5
seconds. The individual WDT pins will go Hi-Z and
be pulled up by external resistors.
Data error (noise margin induced or otherwise)
occurs during a write command.
Incoming checksum will not agree with the
incoming message when read in by any
individual LTC3300-1 in the stack.
Since the CRC remainder will not be zero, the
LTC3300-1 will not execute the write command,
even if an execute command is given. All
balancers with nonzero remainders will be off.
Data error (noise margin induced or otherwise)
occurs during a read command.
Outgoing checksum (calculated by
the LTC3300-1) will not agree with the
outgoing message when read in by the host
microprocessor.
Since the CRC remainder (calculated by the
host) will not be zero, the data cannot be trusted.
All balancers will remain in the state of the last
previously successful write.
APPLICATIONS INFORMATION
Fault Protection
Care should always be taken when using high energy
sources such as batteries. There are numerous ways
that systems can be misconfigured when considering
the assembly and service procedures that might affect a
battery system during its useful lifespan. Table 9 shows
the various situations that should be considered when
planning protection circuitry. The first four scenarios
are to be anticipated during production and appropriate
protection is included within the LTC3300-1 device itself.
