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LTC3300IUK-1#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
LTC3300-1
4
33001fb
For more information www.linear.com/LTC3300-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T
A
= 25°C. (Note 2) BOOST
+
= 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V
–
= 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
Q_EXTRA
Supply Current Extra
(Serial I/O in Current Mode)
Additional Current Measured at C6, V
MODE
= V
–
(CSBI Logic Low, SCKI and SDI Both Logic High;
Refer to I
IL1
, I
IH1
, I
OH1
, I
OL1
Specs)
3.75 mA
V
CELL|MIN
Minimum Cell Voltage (Rising)
Required for Primary Gate Drive
Cn to Cn – 1 Voltage to Balance Cn, n = 2 to 6
C1 Voltage to Balance C1
Cn + 1 to Cn Voltage to Balance Cn, n = 1 to 5
BOOST
+
to C6 Voltage to Balance C6, BOOST = V
–
l
l
l
l
1.8
1.8
1.8
1.8
2
2
2
2
2.2
2.2
2.2
2.2
V
V
V
V
V
CELL|MIN(HYST)
V
CELL|MIN
Comparator Hysteresis 70 mV
V
CELL|MAX
Maximum Cell Voltage (Rising)
Before Disabling Balancing
C1, Cn to Cn – 1 Voltage to Balance Any Cell,
n = 2 to 6
l
4.7 5 5.3 V
V
CELL|MAX(HYST)
V
CELL|MAX
Comparator Hysteresis 0.5 V
V
CELL|RECONNECT
Maximum Cell Voltage (Falling) to
Re-Enable Balancing
l
4.25 V
V
REG
Regulator Pin Voltage 9V ≤ C6 ≤ 36V, 0mA ≤ I
LOAD
≤ 20mA
l
4.4 4.8 5.2 V
V
REG|POR
V
REG
Voltage (Rising) for
Power-On Reset
4.0 V
V
REG|MIN
Minimum V
REG
Voltage (Falling)
for Secondary Gate Drive
V
REG
Voltage to Balance Cn, n = 1 to 6
l
3.8 V
I
REG_SC
Regulator Pin Short Circuit Current
Limit
V
REG
= 0V 55 mA
V
RTONP
RTONP Servo Voltage R
RTONP
= 20kΩ
l
1.158 1.2 1.242 V
V
RTONS
RTONS Servo Voltage R
RTONS
= 15kΩ
l
1.158 1.2 1.242 V
I
WDT_RISING
WDT Pin Current, Balancing R
TONS
= 15kΩ, WDT = 0.5V
l
72 80 88 µA
I
WDT_FALLING
WDT Pin Current as a Percentage
of I
WDT_RISING
, Secondary OV
R
TONS
= 15kΩ, WDT = 2V
l
85 87.5 90 %
V
PEAK_P
Primary Winding Peak Current
Sense Voltage
I1P
InP to Cn – 1, n = 2 to 6
l
l
45
45
50
50
55
55
mV
mV
V
PEAK_P
Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100%
l
±1.7 ±5 %
V
PEAK_S
Secondary Winding Peak Current
Sense Voltage
I1S
InS to Cn – 1, n = 2 to 6, CTRL = 0 Only
l
l
45
45
50
50
55
55
mV
mV
V
PEAK_S
Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100%
l
±0.5 ±3 %
V
ZERO_P
Primary Winding Zero Current
Sense Voltage (Note 5)
I1P
InP to Cn – 1, n = 2 to 6
l
l
–7
–7
–2
–2
3
3
mV
mV
V
ZERO_P
Matching (All 6)
Normalized to Mid-Range V
PEAK_P
±{[(Max – Min)/2]/(V
PEAK_P|MIDRANGE
)} • 100%
(Note 6)
l
±1.7 ±5 %
V
ZERO_S
Secondary Winding Zero Current
Sense Voltage (Note 5)
I1S
InS to Cn
– 1, n = 2 to 6, CTRL = 0 Only
l
l
–12
–12
–7
–7
–2
–2
mV
mV
V
ZERO_S
Matching (All 6)
Normalized to Mid-Range V
PEAK_S
±{[(Max – Min)/2]/(V
PEAK_S|MIDRANGE
)} • 100%
(Note 6)
l
±0.5 ±3 %
R
BOOST_L
BOOST
–
Pin Pull-Down R
ON
Measured at 100mA Into Pin, BOOST = V
REG
2.5 Ω
R
BOOST_H
BOOST
–
Pin Pull-Up R
ON
Measured at 100mA Out of Pin, BOOST = V
REG
4 Ω
T
SD
Thermal Shutdown Threshold
(Note 7)
Rising Temperature 155 °C
T
HYS
Thermal Shutdown Hysteresis 10 °C
Timing Specifications
t
r_P
Primary Winding Gate Drive Rise
Time (10% to 90%)
G1P Through G6P, C
GATE
= 2500pF 35 70 ns
t
f_P
Primary Winding Gate Drive Fall
Time (90% to 10%)
G1P Through G6P, C
GATE
= 2500pF 20 40 ns
LTC3300-1
5
33001fb
For more information www.linear.com/LTC3300-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T
A
= 25°C. (Note 2) BOOST
+
= 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V
–
= 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
r_S
Secondary Winding Gate Drive
Rise Time (10% to 90%)
G1S, C
GATE
= 2500pF
G2S Through G6S, CTRL = 0 Only, C
GATE
= 2500pF
30
30
60
60
ns
ns
t
f_S
Secondary Winding Gate Drive Fall
Time (90% to 10%)
G1S, C
GATE
= 2500pF
G2S Through G6S, CTRL = 0 Only, C
GATE
= 2500pF
20
20
40
40
ns
ns
t
ONP|MAX
Primary Winding Switch Maximum
On-Time
R
RTONP
= 20kΩ (Measured at G1P-G6P)
l
6 7.2 8.4 µs
t
ONP|MAX
Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100%
l
±1 ±4 %
t
ONS|MAX
Secondary Winding Switch
Maximum On-Time
R
RTONS
= 15kΩ (Measured at G1S-G6S)
l
1 1.2 1.4 µs
t
ONS|MAX
Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100%
l
±1 ±4 %
t
DLY_START
Delayed Start Time After New/
Different Balance Command or
Recovery from Voltage/Temp Fault
2 ms
Voltage Mode Timing Specifications
t
1
SDI Valid to SCKI Rising Setup Write Operation
l
10 ns
t
2
SDI Valid from SCKI Rising Hold Write Operation
l
250 ns
t
3
SCKI Low
l
400 ns
t
4
SCKI High
l
400 ns
t
5
CSBI Pulse Width
l
400 ns
t
6
SCKI Rising to CSBI Rising
l
100 ns
t
7
CSBI Falling to SCKI Rising
l
100 ns
t
8
SCKI Falling to SDO Valid Read Operation
l
250 ns
f
CLK
Clock Frequency
l
1 MHz
t
WD1
Watchdog Timer Timeout Period WDT Assertion Measured from Last Valid
Command Byte
l
0.75 1.5 2.25 second
t
WD2
Watchdog Timer Reset Time WDT Negation Measured from Last Valid
Command Byte
l
1.5 5 µs
Current Mode Timing Specifications
t
PD1
CSBI to CSBO Delay C
CSBO
= 150pF
l
600 ns
t
PD2
SCKI Rising to SCKO Delay C
SCKO
= 150pF
l
300 ns
t
PD3
SDI to SDOI Delay C
SDOI
= 150pF, Command Byte
l
300 ns
t
PD4
SCKI Falling to SDOI Valid C
SDOI
= 150pF, Write Balance Command
l
300 ns
t
PD5
SCKI Falling to SDI Valid C
SDI
= 150pF, Read Operation
l
300 ns
t
SCKO
SCKO Pulse Width C
SCKO
= 150pF 100 ns
Voltage Mode Digital I/O Specifications
V
IH
Digital Input Voltage High Pins CSBI, SCKI, SDI; V
MODE
= V
REG
Pins CTRL, BOOST, V
MODE
, TOS
Pin WDT
l
l
l
V
REG
– 0.5
V
REG
– 0.5
2
V
V
V
V
IL
Digital Input Voltage Low Pins CSBI, SCKI, SDI; V
MODE
= V
REG
Pins CTRL, BOOST, V
MODE
, TOS
Pin WDT
l
l
l
0.5
0.5
0.8
V
V
V
I
IH
Digital Input Current High Pins CSBI, SCKI, SDI; V
MODE
= V
REG
Pins CTRL, BOOST, V
MODE
, TOS
Pin WDT, Timed Out
–1
–1
–1
0
0
0
1
1
1
µA
µA
µA
I
IL
Digital Input Current Low Pins CSBI, SCKI, SDI; V
MODE
= V
REG
Pins CTRL, BOOST, V
MODE
, TOS
Pin WDT, Not Balancing
–1
–1
–1
0
0
0
1
1
1
µA
µA
µA
LTC3300-1
6
33001fb
For more information www.linear.com/LTC3300-1
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3300-1 is tested under pulsed load conditions such
that T
J
≈ T
A
. The LTC3300I-1 is guaranteed over the –40°C to 125°C
operating junction temperature range and the LTC3300H-1 is guaranteed
over the –40°C to 150°C operating junction temperature. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors. The junction
temperature (T
J
, in °C) is calculated from the ambient temperature
(T
A
, in °C) and power dissipation (P
D
, in Watts) according to the formula:
T
J
= T
A
+ (P
D
• θ
JA
)
where θ
JA
(in °C/W) is the package thermal impedance.
Note 3: When balancing more than one cell at a time, the individual cell
supply currents can be calculated from the values given in the table as
follows: First add the appropriate table entries cell by cell for the balancers
that are on. Second, for each additional balancer that is on, subtract 70µA
from the resultant sums for C1, C2, C3, C4, and C5, and 450µA from the
resultant sum for C6. For example, if all six balancers are on, the resultant
current for C1 is [250 – 70 + 70 + 70 + 70 + 70 – 5(70)]µA = 110µA and
for C6 is [560 + 560 + 560 + 560 + 560 + 740 – 5(450)]µA = 1290µA.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency during active balancing. See Gate
Drivers/Gate Drive Comparators and Voltage Regulator in the Operation
section for more information on estimating these currents.
Note 5: The zero current sense voltages given in the table are DC
thresholds. The actual zero current sense voltage seen in application will
be closer to zero due to the slew rate of the winding current and the finite
delay of the current sense comparator.
Note 6: The mid-range value is the average of the minimum and maximum
readings within the group of six.
Note 7: This IC includes overtemperature protection intended to protect
the device during momentary overload conditions. The maximum junction
temperature may be exceeded when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may result in device degradation or failure.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OL
Digital Output Voltage Low Pin SDO, Sinking 500µA; V
MODE
= V
REG
; Read
l
0.3 V
I
OH
Digital Output Current High Pin SDO at 6V
l
100 nA
Current Mode Digital I/O Specifications
I
IL1
Digital Input Current Low Pin CSBI; V
MODE
= V
–
Pin SCKI; V
MODE
= V
–
Pin SDI, V
MODE
= V
–
, Write
Pin SDOI, TOS = V
–
, Read
l
l
l
l
–1500
–5
–5
0
–1250
–2.5
–2.5
2.5
–1000
0
0
5
µA
µA
µA
µA
I
IH1
Digital Input Current High Pin CSBI; V
MODE
= V
–
Pin SCKI; V
MODE
= V
–
Pin SDI, V
MODE
= V
–
, Write
Pin SDOI, TOS = V
–
, Read
l
l
l
l
–5
–1500
–1500
1000
–2.5
–1250
–1250
1250
0
–1000
–1000
1500
µA
µA
µA
µA
I
OH1
Digital Output Current High Pin CSBO; TOS = V
–
Pin SCKO; TOS = V
–
Pin SDOI, TOS = V
–
, Write
Pin SDI, V
MODE
= V
–
, Read
l
l
l
l
0
1000
1000
2.5
1250
1250
5
–1000
µA
µA
µA
µA
I
OL1
Digital Output Current Low Pin CSBO; TOS = V
–
Pin SCKO; TOS = V
–
Pin SDOI, TOS = V
–
, Write
Pin SDI, V
MODE
= V
–
, Read
l
l
l
l
1000
0
0
–5
1250
2.5
2.5
5
5
µA
µA
µA
µA
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T
A
= 25°C. (Note 2) BOOST
+
= 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V
–
= 0V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

LTC3300IUK-1#PBF

Mfr. #:
Buy LTC3300IUK-1#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Hi Eff Bi-dir Multicell Bat Balancer
Lifecycle:
New from this manufacturer.
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