LTC3300-1
19
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For more information www.linear.com/LTC3300-1
OPERATION
Figure 4. Diagram of Power Transfer Interleaving Through the
Stack, Transformer Connections for High Voltage Stacks
Balancing High Voltage Battery Stacks
Balancing series connected batteries which contain >>12
cells in series requires interleaving of the transformer sec-
ondary connections in order to achieve full stack balancing
while limiting the breakdown voltage requirements of the
primary- and secondar
y-side power FETs. Figure 4 shows
typical interleaved transformer connections for a multicell
battery stack in the generic sense, and Figure 5 for the
specific case of an 18-cell stack. In these examples, the
secondary side of each transformer is connected to the
top of the cell that is 12 positions higher in the stack than
the bottom of the lowest voltage cell in each LTC3300-1
sub-stack. For the top most LTC3300-1 in the stack, it is
not possible to connect the secondary side of the trans-
former across 12 cells. Instead, it is connected to the top
of the stack, or effectively across only 6 cells. Interleaving
in this fashion allows charge to transfer between 6-cell
sub-stacks throughout the entire battery stack.
Max On-Time Volt-Sec Clamps
The LTC3300-1 contains programmable fault protection
clamps which limit the amount of time that current is
allowed to ramp in either the primary or secondary wind
-
ings in the event of a shorted sense resistor. Maximum
on time for all primar
y connections (active during cell
discharging) and all secondar
y connections (active during
cell charging) is individually programmable by connecting
resistors from the R
TONP
and R
TONS
pins to V
according
to the following equations:
t
ON(MAX)|PRIMARY
= 7.2µs
R
TONP
20kΩ
t
ON(MAX)|SECONDARY
= 1.2µs
R
TONS
15kΩ
For more information on selecting the appropriate
maximum on-times, refer to the Applications Information
section.
To defeat this function, short the appropriate R
TON
pin(s)
to V
REG
.
+
+
LTC3300-1
POWER STAGES
LTC3300-1
POWER STAGES
FROM CELL N-12
SECONDARY
TO CELL 24
PRI SEC
+
+
+
+
+
+
LTC3300-1
POWER STAGES
SEC PRI
SEC PRI
+
+
CELL 18
CELL 13
CELL 6
CELL 7
CELL 12
CELL N-6
CELL N
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
33001 F04
LTC3300-1
POWER STAGES
PRI
TOP
SEC
+
+
LTC3300-1
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For more information www.linear.com/LTC3300-1
OPERATION
Figure 5. 18-Cell Active Balancer Showing Power Connections,
Interleaved Transformer Secondaries and BOOST
+
Rail Generation Up the Stack
1:1
10µH
TO TRANSFORMER
SECONDARIES OF
BALANCERS 14 TO 18
10µH
CELL 18
25mΩ
25mΩ
C1
C6
G1P
I1P
G1S
I1S
V
REG
V
LTC3300-1
BOOST
BOOST
+
BOOST
0.1µF
6.8Ω
1:1
10µH
TO TRANSFORMER
SECONDARIES OF
BALANCERS 8 TO 12
10µH
25mΩ
25mΩ
C1
C6
G1P
I1P
G1S
I1S
V
LTC3300-1
BOOST
BOOST
+
1:1
10µH
TO TRANSFORMER
SECONDARIES OF
BALANCERS 2 TO 6
10µH
25mΩ
25mΩ
33001 F05
C1
C6
G1P
I1P
G1S
I1S
V
LTC3300-1
BOOST
BOOST
+
+
CELL 13
+
CELL 12
+
CELL 7
+
CELL 6
+
CELL 1
+
10µF
10µF
10µF
LTC3300-1
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For more information www.linear.com/LTC3300-1
OPERATION
Gate Drivers/Gate Drive Comparators
All secondary-side gate drivers (G1S through G6S) are
powered from the V
REG
output, pulling up to 4.8V when
on and pulling down to V
when off. All primary-side
gate drivers (G1P through G6P) are powered from their
respective cell voltage and the next cell voltage higher in
the stack (see Table 1). An individual cell balancer will only
be enabled if its corresponding cell voltage is greater than
2V and the cell voltage of the next higher cell in the stack
is also greater than 2V. For the G6P gate driver output,
the next higher cell in the stack is C1 of the next higher
LTC3300-1 in the stack (if present) and is only used if the
boosted gate drive is disabled (by connecting BOOST =
V
). If the boosted gate drive is enabled (by connecting
BOOST = V
REG
), only the C6 cell voltage is looked at to
enable balancing of Cell 6. In the case of the topmost
LTC3300-1 in the stack, the boosted gate drive must be
enabled. The boosted gate drive requires an external diode
from C6 to BOOST
+
and a boost capacitor from BOOST
+
to
BOOST
. For information on selecting these components,
refer to the Applications Information section. Also note
that the dynamic supply current referred to in Note 4 of
the Electrical Characteristics table adds to the terminal
currents of the pins indicated in the Voltage When Off and
Voltage When On columns of Table 1.
The gate drive comparators have a DC hysteresis of 70mV.
For improved noise immunity, the inputs are internally
low pass filtered and the outputs are filtered so as to
not transition unless the internal comparator state is
unchanged for 3µs to 6µs (typical). If insufficient gate drive
is detected while active balancing is in progress (perhaps,
for example, if the stack is under heavy load), the affected
balancer(s) and only the affected balancer(s) will
shut off.
The balance command remains stored in memory, and
active balancing will resume where it left off if sufficient
gate drive is subsequently restored. This can happen if,
for example, the stack is being charged.
Cell Overvoltage Comparators
In addition to sufficient gate drive being required to enable
balancing, there are additional comparators which disable
all active balancing if any of the six individual cell voltages
is greater than 5V. These comparators have a DC hysteresis
of 500mV. For improved noise immunity, the inputs are
internally low pass filtered and the outputs are filtered so
as to not transition unless the internal comparator state
is unchanged for 3µs to 6µs (typical). If any cell voltage
goes overvoltage while active balancing is in progress,
all active balancers will shut off. The balance command
remains stored in memory, and active balancing will resume
where if left off if the cell voltage subsequently comes back
in range. These comparators will protect the LTC3300-1 if
a connection to a battery is lost while balancing and the
cell voltage is still increasing as a result of that balancing.
Table 1
DRIVER OUTPUT VOLTAGE WHEN OFF VOLTAGE WHEN ON GATE DRIVE REQUIRED TO ENABLE BALANCING
G1P V- C2 (C2 – C1) ≥ 2V and (C1 – V
) ≥2V
G2P C1 C3 (C3 – C2) ≥ 2V and (C2 – C1) ≥2V
G3P C2 C4 (C4 – C3) ≥ 2V and (C3 – C2) ≥2V
G4P C3 C5 (C5 – C4) ≥ 2V and (C4 – C3) ≥2V
G5P C4 C6 (C6 – C5) ≥ 2V and (C5 – C4) ≥2V
G6P C5 If BOOST = V
REG
: BOOST+ (Generated) (C6 – C5) ≥ 2V
If BOOST = V
: BOOST
+
= C7* (C7* – C6) ≥ 2V and (C6 – C5) ≥ 2V
*C7 is equal to C1 of the next higher LTC3300-1 in the stack if this connection is used.

LTC3300IUK-1#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Hi Eff Bi-dir Multicell Bat Balancer
Lifecycle:
New from this manufacturer.
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