LTC3300IUK-1#PBF Datasheet LTC3300ILXE-1#PBF, LTC3300IUK-1#PBF, LTC3300HUK-1#PBF | P28-P30

LTC3300-1

33001fb

For more information www.linear.com/LTC3300-1

OPERATION

The first 12 bits of the 16-bit balance command are used

to indicate which balancer (or balancers) is active and in

which direction (charge or discharge). Each of the 6 cell

balancers is controlled by 2 bits of this data per Table 5.

The balancing algorithm for a given cell is:

Charge Cell n: Ramp up to I

PEAK

in secondary winding,

ramp down to I

ZERO

in primary winding. Repeat.

Discharge Cell n (Synchronous): Ramp up to Ipeak in

primary winding, ramp down to I

ZERO

in secondary

winding. Repeat.

Table 5. Cell Balancer Control Bits

Dn A Dn B Balancing Action (n = 1 to 6)

0 0 None

0 1 Discharge Cell n (Nonsynchronous)

1 0 Discharge Cell n (Synchronous)

1 1 Charge Cell n

For nonsynchronous discharging of cell n, both the sec-

ondary winding gate drive and (zero) current sense amp

are disabled. The secondary current will conduct either

through the body diode of the secondar

y switch (if pres

ent) or through a substitute Schottky diode. The primary

will only turn on again after the secondary winding Volt-

sec clamp times out. In a bidirectional application with a

secondary switch, it may be possible to achieve slightly

higher discharge efficiency by opting for nonsynchronous

discharge mode (if the gate charge savings exceed the

added diode drop losses) but the balancing current will be

less predictable because the secondary winding Volt-sec

clamp must be set longer than the expected time for the

current to hit zero in order to guarantee no current reversal.

In the case where a Schottky diode replaces the secondary

switch, it is possible to build a undirectional discharge-only

balancing application charging an isolated auxiliary cell

as shown in Figure 19 in the Typical Applications section.

In the CTRL = 1 application of Figure 7 employing a single

transformer which can only balance one cell at a time, any

command requesting simultaneous balancing of more than

one cell will be ignored. All active balancing will be turned

off if an Execute Balance Command is subsequently written.

The last 4 bits of the 16-bit balance command are used

for packet error checking (PEC). The 16 bits of write data

(12-bit message plus 4-bit CRC) are input to a cyclic re

dundancy check (CRC) block employing the International

Telecommunication Union CRC-4 standard characteristic

polynomial:

+ x + 1

In the write data, the 4-bit CRC appended to the message

must be selected such that the remainder of the CRC divi

sion is zero. Note that the CRC bits in the Write Balance

Command are inverted. This was done so that an “all zeros”

command is invalid. The LTC3300-1 will ignore the write

data if the remainder is not zero and the internal command

holding register will be cleared which can be verified on

readback. The current balance command being executed

(from the last previously successful write) will continue,

but all active balancing will be turned off if an Execute Bal

ance Command is subsequently written. For information

on how to calculate the CRC including an example, refer

to the Applications Information section.

Readback Balance Command

The bit mapping for Readback Balance Command is identi

cal to that for Write Balance Command. If the command

bits program Readback Balance Command, successive

16-bit

previously

written data (latched in 12-bit message

plus newly calculated 4-bit CRC) are shifted out in the

same order bitwise (MSB first) starting with the lowest

LTC3300-1 in the stack and proceeding up the stack. Thus,

the sequence of outcoming data during readback is:

Command data (bottom chip), Command data (2nd chip

from bottom), …, Command data (top chip)

This command allows for microprocessor verification of

written commands before executing. Note that the CRC

bits in the Readback Balance Command are also inverted.

This was done so that an “all zeros” readback is invalid.

LTC3300-1

33001fb

For more information www.linear.com/LTC3300-1

Read Balance Status

If the command bits program Read Balance Status, suc-

cessive 16-bit status data (12 bits of data plus associated

4-bit CRC) are shifted out MSB first per T

able 6. Similar

a Readback Balance Command, the last 4 bits in each

16-bit balance status are used for error detection. The

first 12 bits of the status are input to a cyclic redundancy

check (CRC) block employing the same characteristic

polynomial used for write commands. The LTC3300-1

will calculate and append the appropriate 4-bit CRC to

the outgoing 12-bit message which can then be used for

microprocessor error checking. The sequence of outcom

ing data during readback is:

Status data (bottom chip), Status data (2nd chip from

bottom), …, Status data (top chip)

Note that the

CRC bits in the Read Balance Status are

inverted. This was done so that an “all zeros” readback

is invalid.

The first 6 bits of the read balance status indicate if there

is sufficient gate drive for each of the 6 balancers. These

bits correspond to the right-most column in Table 1, but

can only be logic high for a given balancer following an

execute command involving that same balancer. If a bal

ancer is not active, its Gate Drive OK bit will be logic low.

The 7th, 8th, and 9th bits in the read balance status indicate

that all 6 cells are not over

voltage, that the transformer

secondary is not overvoltage, and that the LTC3300-1 die

is not overtemperature, respectively. These 3 bits can only

be logic high following an execute command involving at

least one balancer. The 10th, 11th, and 12th bits in the

OPERATION

read balance status are currently not used and will always

be logic zero. As an example, if balancers 1 and 4 are both

active with no voltage or temperature faults, the 12-bit

read balance status should be 100100111000.

Execute Balance Command

If the command bits program Execute Balance Command,

the last successfully written and latched in balance com

mand will be executed immediately. All subsequent (write)

data will be ignored until CSBI transitions high and then

low again.

Pause/Resume Balancing (via SPI Port)

The LTC3300-1 provides a simple means to interrupt bal

ancing in progress (stack wide) and then restart without

having

to rewrite the previous balance command to all

LTC3300-1 ICs in the stack. To pause balancing, simply

write an 8-bit Execute Balance Command with the parity

bit flipped: 10101110. To resume balancing, simply write

an Execute Balance Command with the correct parity:

10101111. This feature is useful if precision cell voltage

measurements want to be performed during balancing

with the stack “quiet.” Immediate pausing of balancing

in progress will occur for any 8-bit Command Byte with

incorrect parity.

The restart time is typically 2ms which is the same as the

delayed start time after a new or different balance command

DLY_START

). It is measured from the 8th rising SCKI edge

until the balancer turns on and is illustrated in G27 in the

Typical Performance Characteristics section.

Table 6. Read Balance Status Data Bit Mapping (defaults to 0x000F in Reset State)

Gate

Drive 1

(MSB)

Gate

Drive 2

Gate

Drive 3

Gate

Drive 4

Gate

Drive 5

Gate

Drive 6

Cells

Not OV

Sec

Not OV

Temp

0 0 CRC[3] CRC[2] CRC[1] CRC[0]

(LSB)

LTC3300-1

33001fb

For more information www.linear.com/LTC3300-1

APPLICATIONS INFORMATION

External Sense Resistor Selection

The external current sense resistors for both primary

and secondary windings set the peak balancing current

according to the following formulas:

SENSE|PRIMARY

50mV

PEAK _PRI

SENSE|SECONDARY

50mV

PEAK _SEC

Balancer Synchronization

Due to the stacked configuration of the individual synchro-

nous flyback power circuits and the interleaved nature of

the gate drivers, it is possible at higher balance currents

for adjacent and/or penadjacent balancers within a group

of six to sync up. The synchronization will typically be to

the highest frequency of any active individual balancer and

can result in a slightly lower balance current in the other

affected balancer(s). This error will typically be very small

provided that the individual cells are not significantly out

of balance voltage-wise and due to the matched I

PEAK

ZERO

’s and matched power circuits. Balancer synchro-

nization can be reduced by lowpass filtering the primary

and/or secondar

y current sense signals with a simple RC

network as shown in Figure 10. A good starting point for

the RC time constant is one-tenth of the on-time of the

associated switch (primary or secondary). In the case

of I

PEAK

sensing, phase lag associated with the lowpass

filter will result in a slightly lower voltage seen by the

LTC3300-1 compared to the true sense resistor voltage.

This error can be compensated for by selecting the R value

to add back this same drop using the typical current value

of 20µA out of the LTC3300-1 current sense pins at the

comparator trip point.

Setting Appropriate Max On-Times

The primary and secondary winding volt-second clamps

are intended to be used as a current runaway protection

feature and not as a substitute means of current control

replacing the sense resistors. In order to not interfere with

normal I

PEAK

ZERO

operation, the maximum on times must

be set longer than the time required to ramp to I

PEAK

(or

ZERO

) for the minimum cell voltage seen in the application:

ON(MAX)|PRIMARY

> L

PRI

• I

PEAK_PRI

CELL(MIN)

ON(MAX)|SECONDARY

> L

PRI

• I

PEAK_SEC

• T/(S • V

CELL(MIN)

)

These can be further increased by 20% to account for

manufacturing tolerance in the transformer winding

inductance and by 10% to account for I

PEAK

variation.

LTC3300-1

n = 2 TO 6

20µA

SNS

33001 F10

G1P/GnP/G1S/GnS

I1P/InP/I1S/InS

–

/Cn – 1/V

–

Figure 10. Using an RC Network to Filter Current Sense Inputs to

the LTC3300-1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P46

LTC3300IUK-1#PBF

Mfr. #:

Buy LTC3300IUK-1#PBF

Manufacturer:

Analog Devices / Linear Technology

Description:

Battery Management Hi Eff Bi-dir Multicell Bat Balancer

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

LTC3300IUK-1#PBF

LTC3300IUK-1#PBF

Products related to this Datasheet