PCA85233UG/2DA/Q1Z Datasheet PCA85233UG/2DA/Q1Z | P25-P27

Product data sheet Rev. 4 — 6 May 2015 25 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

The START and STOP conditions are shown in Figure 15.

8.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 16

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I

C-bus is shown in Figure 17.

Fig 15. Definition of START and STOP conditions

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Product data sheet Rev. 4 — 6 May 2015 26 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

8.5 I

C-bus controller

The PCA85233 acts as an I

C-bus slave receiver. It does not initiate I

C-bus transfers or

transmit data to an I

C-bus master receiver. The only data output from the PCA85233 are

the acknowledge signals from the selected devices. Device selection depends on the

C-bus slave address, on the transferred command data, and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0 and A1 are normally tied

to V

which defines the hardware subaddress 0. In multiple device applications A0

and A1 are tied to V

or V

using a binary coding scheme, so that no two devices with a

common I

C-bus slave address have the same hardware subaddress.

8.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

8.7 I

C-bus protocol

Two I

C-bus slave addresses (0111 000 and 0111 001) are used to address the

PCA85233. The entire I

C-bus slave address byte is shown in Table 17.

The PCA85233 is a write-only device and will not respond to a read access, therefore bit 0

should always be logic 0. Bit 1 of the slave address byte that a PCA85233 will respond to,

is defined by the level tied to its SA0 input (V

for logic 0 and V

for logic 1).

Fig 17. Acknowledgement on the I

C-bus

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Table 17. I

C slave address byte

Slave address

Bit 7 6 5 4 3 2 1 0

MSB LSB

011100SA0R/W

Product data sheet Rev. 4 — 6 May 2015 27 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

Having two reserved slave addresses allows the following on the same I

C-bus:

• Up to 8 PCA85233 on the same I

C-bus for very large LCD applications

• The use of two types of LCD multiplex drive modes on the same I

C-bus

The I

C-bus protocol is shown in Figure 18. The sequence is initiated with a START

condition (S) from the I

C-bus master which is followed by one of the available PCA85233

slave addresses. All PCA85233 with the same SA0 level acknowledge in parallel to the

slave address. All PCA85233 with the alternative SA0 level ignore the whole I

C-bus

transfer.

After acknowledgement, the control byte is sent, defining if the next byte is a RAM or

command information. The control byte also defines if the next byte is a control byte or

further RAM or command data (see Figure 19

and Table 18). In this way it is possible to

configure the device and then fill the display RAM with little overhead.

Fig 18. I

C-bus protocol

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Fig 19. Control byte format

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PCA85233UG/2DA/Q1Z

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Buy PCA85233UG/2DA/Q1Z

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NXP Semiconductors

Description:

LCD Drivers PCA85233UG/WLCSP201//2DA/Q1/DIE 3 WAFFLE CARRIERS

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PCA85233UG/2DA/Q1Z