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PCA85233UG/2DA/Q1Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54
PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 7 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
or equals an external clock frequency f
clk(ext)
:
(2)
7.2.1.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to V
SS
. In this case the output
from pin CLK provides the clock signal for any cascaded PCA85233 in the system.
7.2.1.2 External clock
Connecting pin OSC to V
DD
enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.2.2 Frame frequency
The clock frequency f
clk
determines the LCD frame frequency f
fr
and is calculated as
follows:
(3)
The internal clock frequency f
clk
can be selected using pin FF. As a result 2 frame
frequencies are available: 150 Hz or 220 Hz (typical), see Table 11
.
[1] FF has no effect when an external clock is used but must not be left floating.
The timing of the PCA85233 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC
) maintains the correct timing
relationship between all the PCA85233 in the system.
7.2.3 Blinking
The display blink capabilities of the PCA85233 are very versatile. The whole display can
blink at frequencies selected by the blink-select command (see Table 10
). The blink
frequencies are derived from the clock frequency. The ratios between the clock and blink
frequencies depend on the blink mode selected (see Table 12
).
f
clk
f
clk ext
=
Table 11. LCD frame frequencies
Pin FF tied to
[1]
Typical clock frequency (Hz) LCD frame frequency (Hz)
V
DD
3600 150
V
SS
5280 220
f
fr
f
clk
24
--------
=
PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 8 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
An additional feature is for an arbitrary selection of LCD segments to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can blink by selectively changing the display RAM data at fixed time
intervals.
If the entire display can blink at a frequency other then the typical blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 6
).
7.3 Display RAM
The display RAM is a static 80 4 bit RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD segments/elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map, Figure 4
, shows rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment
outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second,
third and fourth row of the display RAM are time-multiplexed with BP0,
BP1, BP2, and BP3 respectively.
Table 12. Blink frequencies
Blink mode Operating mode ratio Blink frequency with respect to f
clk
(typical) Unit
f
clk
= 3.600 kHz f
clk
= 5.280 kHz
off - blinking off blinking off Hz
14.76.9Hz
22.33.4Hz
31.21.7Hz
f
clk
1536
------------
f
clk
3072
------------
PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 9 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
When display data is transmitted to the PCA85233, the received display bytes are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and depending on the current multiplex drive mode the bits are stored singularly,
in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment
display showing all drive modes is given in Figure 5
; the RAM filling organization depicted
applies equally to other LCD types.
The following applies to Figure 5
:
• In static drive mode the eight transmitted data bits are placed into row 0 as one byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as four successive 2-bit RAM words.
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.3.3
).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
The display RAM bitmap shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Fig 4. Display RAM bitmap
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54

PCA85233UG/2DA/Q1Z

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Buy PCA85233UG/2DA/Q1Z
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers PCA85233UG/WLCSP201//2DA/Q1/DIE 3 WAFFLE CARRIERS
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