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PCA85233UG/2DA/Q1Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54
PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 4 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
6.2 Pin description
[1] The substrate (rear side of the die) is at V
SS
potential and should be electrically isolated.
Viewed from active side. For mechanical details, see Figure 27
.
Fig 3. Pin configuration for PCA85233
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Table 4. Pin description overview
Input or input/output pins must always be at a defined level (V
SS
or V
DD
) unless otherwise specified.
Symbol Pin Description
SDAACK 1 to 3 I
2
C-bus acknowledge output
SDA 4 to 6 I
2
C-bus serial data input
SCL 7 to 9 I
2
C-bus serial clock input
CLK 10 clock input and output
V
DD
11 to 13 supply voltage
SYNC
14 cascade synchronization input or output; if not
used it must be left open
OSC 15 oscillator select
FF 16 frame frequency select
A0, A1 17, 18 subaddress input
T1 19 dedicated testing pin; to be tied to V
SS
in
application mode
SA0 20 I
2
C-bus slave address input
V
SS
[1]
21 to 23 ground supply voltage
V
LCD
24 to 26 LCD supply voltage
BP2, BP0, BP3, and BP1 27, 28, 109 and 110 LCD backplane output
S0 to S79 29 to 108 LCD segment output
D1 to D9 - dummy pins
PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 5 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
7. Functional description
7.1 Commands of PCA85233
The command decoder identifies command bytes that arrive on the I
2
C-bus. The
commands available to the PCA85233 are defined in Table 5
.
[1] The possibility to disable the display allows implementation of blinking under external control.
[2] The display is disabled by setting all backplane and segment outputs to V
LCD
.
[3] Not applicable for static drive mode.
Table 5. Definition of commands
Command Operation code Reference
Bit 7 6 5 4 3 2 1 0
mode-set 1 1 0 0 E B M[1:0] Tabl e 6
load-data-pointer 0 P[6:0] Tabl e 7
device-select 1 1 1 0 0 0
A[1:0]
Tabl e 8
bank-select 1 1 1 1 1 0 I O Tabl e 9
blink-select 1 1 1 1 0 AB BF[1:0] Tabl e 10
Table 6. Mode-set command bit description
Bit Symbol Value Description
7 to 4 - 1100 fixed value
3E display status
[1]
0 disabled (blank)
[2]
1 enabled
2B LCD bias configuration
[3]
0
1
⁄
3
bias
1
1
⁄
2
bias
1 to 0 M[1:0] LCD drive mode selection
01 static; 1 backplane
10 1:2 multiplex; 2 backplanes
11 1:3 multiplex; 3 backplanes
00 1:4 multiplex; 4 backplanes
Table 7. Load-data-pointer command bit description
See Section 7.3.1
.
Bit Symbol Value Description
7 - 0 fixed value
6 to 0 P[6:0] 0000000 to
1001111
data pointer
7-bit binary value of 0 to 79, transferred to the data pointer to
define one of 80 display RAM addresses
PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 6 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
[1] The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes.
[1] Normal blinking can only be selected in multiplex drive mode 1:3 or 1:4.
[2] For the blink frequencies, see Table 12
.
7.2 Clock and frame frequency
7.2.1 Oscillator
The internal logic and the LCD drive signals of the PCA85233 are timed by a frequency
f
clk
which either is derived from the built-in oscillator frequency f
osc
:
(1)
Table 8. Device-select command bit description
See Section 7.3.2.
Bit Symbol Value Description
7 to 2 - 111000 fixed value
1 to 0 A[1:0] 00 to 11 device selection
2-bit binary value of 0 to 3, transferred to the subaddress
counter to define one of 4 hardware subaddresses
Table 9. Bank-select command bit description
[1]
See Section 7.3.5 and Section 7.3.6.
Bit Symbol Value Description
Static 1:2 multiplex
7 to 2 - 111110 fixed value
1I input bank selection: storage of arriving display data
0 RAM row 0 RAM rows 0 and 1
1 RAM row 2 RAM rows 2 and 3
0O output bank selection: retrieval of LCD display data
0 RAM row 0 RAM rows 0 and 1
1 RAM row 2 RAM rows 2 and 3
Table 10. Blink-select command bit description
See Section 7.2.3
.
Bit Symbol Value Description
7 to 3 - 11110 fixed value
2AB blink mode selection
[1]
0 normal blinking
1 blinking by alternating display RAM banks
1 to 0 BF[1:0] blink frequency selection
[2]
00 off
01 1
10 2
11 3
f
clk
f
osc
64
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=
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54

PCA85233UG/2DA/Q1Z

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NXP Semiconductors
Description:
LCD Drivers PCA85233UG/WLCSP201//2DA/Q1/DIE 3 WAFFLE CARRIERS
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