PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 37 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
For display sizes that are not multiple of 320 segments/elements, a mixed cascaded
system can be considered containing only devices like PCA85233 and PCA85132.
Depending on the application, one must take care of the software command and pin
connection compatibility.
Only one master but multiple slaves are allowed in a cascade. All devices in the cascade
have to use the same clock whether it is supplied externally or provided by the master.
The SYNC
line is provided to maintain the correct synchronization between all cascaded
PCA85233. The only time that SYNC
is likely to be needed is if synchronization is
accidentally lost (e.g. by noise in adverse electrical environments or by the definition of a
multiplex drive mode when PCA85233 with different SA0 levels are cascaded).
SYNC
is organized as an input/output pin; The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCA85233 asserts the SYNC
line at
the onset of its last active backplane signal and monitors the SYNC
line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCA85233 to assert
SYNC
. The timing relationships between the backplane waveforms and the SYNC signal
for the various drive modes of the PCA85233 are shown in Figure 26
.
Fig 26. Synchronization of the cascade for the various PCA85233 drive modes
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