PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 31 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
12. Static characteristics
Table 20. Static characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 8.0 V; T
amb
=
40
C to +105
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
DD
supply voltage V
LCD
6.5 V 1.8 - 5.5 V
V
LCD
> 6.5 V 2.5 - 5.5 V
V
LCD
LCD supply voltage V
DD
< 2.5 V 2.5 - 6.5 V
V
DD
2.5 V 2.5 - 8.0 V
I
DD
supply current f
clk(ext)
= 1536 Hz;
V
DD
=5.5V; see Figure 21
[1]
-36A
I
DD(LCD)
LCD supply current f
clk(ext)
= 1536 Hz;
V
DD
=5.5V;V
LCD
=8.0V;
see Figure 21
[1]
-2245A
Logic
V
I
input voltage V
SS
0.5 - V
DD
+ 0.5 V
V
IH
HIGH-level input voltage on pins CLK, SYNC, OSC,
A0, A1, T1, SA0, FF
0.7V
DD
-V
DD
V
V
IL
LOW-level input voltage on pins CLK, SYNC, OSC,
A0, A1, T1, SA0, FF
V
SS
-0.3V
DD
V
V
OH
HIGH-level output voltage 0.8V
DD
--V
V
OL
LOW-level output voltage - - 0.2V
DD
V
I
OH
HIGH-level output current output source current;
on pin CLK;
V
OH
=4.6V; V
DD
=5V
1- - mA
I
OL
LOW-level output current output sink current;
on pin CLK, SYNC
;
V
OL
= 0.4 V; V
DD
=5V
1- - mA
I
L
leakage current on pins OSC, CLK, SCL,
SDA, A0, A1, T1, SA0, FF;
V
I
=V
DD
or V
SS
1- +1A
C
I
input capacitance
[3]
--7pF
I
2
C-bus
[2]
Input on pins SDA and SCL
V
I
input voltage V
SS
0.5 - 5.5 V
V
IH
HIGH-level input voltage 0.7V
DD
-5.5V
V
IL
LOW-level input voltage V
SS
-0.3V
DD
V
C
I
input capacitance
[3]
--7pF
I
OL(SDA)
LOW-level output current
on pin SDA
output sink current;
V
OL
= 0.4 V; V
DD
= 5 V
3- - mA
PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 32 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
[1] LCD outputs are open-circuit; inputs at V
SS
or V
DD
; external clock with 50 % duty factor; I
2
C-bus inactive.
[2] The I
2
C-bus interface of PCA85233 is 5 V tolerant.
[3] Not tested, design specification only.
[4] Outputs measured individually and sequentially.
LCD outputs
V
O
output voltage variation on pins BP0 to BP3; C
bpl
=
35 nF
100 - +100 mV
on pins S0 to S79; C
sgm
= 5
nF
100 - +100 mV
R
O
output resistance V
LCD
= 5 V
on pins BP0 to BP3
[4]
-1.510k
on pins S0 to S79
[4]
-6.013.5k
Table 20. Static characteristics
…continued
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 8.0 V; T
amb
=
40
C to +105
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Conditions: V
DD
= 5.5 V; V
LCD
=8V; T
amb
=27C; all RAM filled with 0.
(1) I
DD(LCD)
.
(2) I
DD
.
Fig 21. Current consumption with respect to external clock frequency
DDD
 
 
 
 
 
I
FONH[W
N+]
,
''''
,
''
$$$
,
''/&'''/&'
,
''/&'
$$$


PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 33 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
13. Dynamic characteristics
Table 21. Dynamic characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 8.0 V; T
amb
=
40
C to +105
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock
Internal: output pin CLK
f
clk
clock frequency FF = V
DD
[1]
[2]
2630 3600 4680 Hz
FF = V
SS
[1]
[2]
3855 5280 6865 Hz
f
fr
frame frequency FF = V
DD
- 150 - Hz
FF = V
SS
- 220 - Hz
f
fr
frame frequency variation FF = V
DD
; see Figure 22 110 150 195 Hz
FF = V
SS
; see Figure 22 161 220 286 Hz
External: input pin CLK
f
clk(ext)
external clock frequency
[2]
800 - 7000 Hz
t
clk(H)
HIGH-level clock time 90 - - s
t
clk(L)
LOW-level clock time 90 - - s
Synchronization: input pin SYNC
t
PD(SYNC_N)
SYNC propagation delay - 30 - ns
t
SYNC_NL
SYNC LOW time 1 - - s
Outputs: pins BP0 to BP3 and S0 to S79
t
PD(drv)
driver propagation delay V
LCD
= 5 V - - 30 s
I
2
C-bus: timing
[3]
Pin SCL
f
SCL
SCL clock frequency - - 400 kHz
t
HIGH
HIGH period of the SCL
clock
0.6 - - s
t
LOW
LOW period of the SCL
clock
1.3 - - s
Pin SDA
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns

PCA85233UG/2DA/Q1Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers PCA85233UG/WLCSP201//2DA/Q1/DIE 3 WAFFLE CARRIERS
Lifecycle:
New from this manufacturer.
Delivery:
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