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PCA85233UG/2DA/Q1Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54
PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 34 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
[1] Typical output duty cycle of 50 %.
[2] The corresponding frame frequency is .
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V
IL
and V
IH
with an
input voltage swing of V
SS
to V
DD
. For I
2
C-bus timings see Figure 24.
Pins SCL and SDA
t
BUF
bus free time between a
STOP and START
condition
1.3 - - s
t
SU;STO
set-up time for STOP
condition
0.6 - - s
t
HD;STA
hold time (repeated)
START condition
0.6 - - s
t
SU;STA
set-up time for a repeated
START condition
0.6 - - s
t
r
rise time of both SDA and
SCL signals
f
SCL
= 400 kHz - - 0.3 s
f
SCL
< 125 kHz - - 1.0 s
t
f
fall time of both SDA and
SCL signals
--0.3s
C
b
capacitive load for each
bus line
--400pF
t
w(spike)
spike pulse width on bus - - 50 ns
Table 21. Dynamic characteristics
…continued
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 8.0 V; T
amb
=
40
C to +105
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
fr
f
clk
24
--------
=
(1) V
DD
=5.5V; FF=V
SS
.
(2) V
DD
=5.5V; FF=V
DD
.
(3) V
DD
=1.8V; FF=V
SS
.
(4) V
DD
=1.8V; FF=V
DD
.
Fig 22. Frame frequency with respect to temperature
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PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 35 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
14. Application information
14.1 Cascaded operation
In large display configurations up to 8 PCA85233 can be recognized on the same I
2
C-bus
by using the 2-bit hardware subaddress (A0 and A1) and the programmable I
2
C-bus slave
address (SA0).
Fig 23. Driver timing waveforms
Fig 24. I
2
C-bus timing waveforms
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PCA85233 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 36 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
When cascaded PCA85233 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCA85233 of the cascade contribute
additional segment outputs. The backplanes can either be connected together to enhance
the drive capability or some can be left open-circuit (such as the ones from the slave in
Figure 25
) or just some of the master and some of the slave will be taken to facilitate the
layout of the display.
Table 22. Addressing cascaded PCA85233
Cluster Bit SA0 Pin A1 Pin A0 Device
10000
011
102
113
21004
015
106
117
(1) Is master (OSC connected to V
SS
).
(2) Is slave (OSC connected to V
DD
).
Fig 25. Cascaded PCA85233 configuration
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54

PCA85233UG/2DA/Q1Z

Mfr. #:
Buy PCA85233UG/2DA/Q1Z
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers PCA85233UG/WLCSP201//2DA/Q1/DIE 3 WAFFLE CARRIERS
Lifecycle:
New from this manufacturer.
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