2015-2016 Microchip Technology Inc. DS20005386B-page 19
PAC1710/20
5.0 SMBUS COMMUNICATION
5.0.1 SMBus START BIT
The SMBus Start bit is defined as a transition of the
SMBus Data line from a logic ‘1’ state to a logic ‘0’ state
while the SMBus Clock line is in a logic ‘1’ state.
5.0.2 SMBus ADDRESS AND RD/WR BIT
The SMBus Address Byte consists of the 7-bit client
address followed by a 1-bit RD/WR
indicator. If this
RD/WR
bit is a logic ‘0’, the SMBus host is writing data
to the client device. If this RD/WR
bit is a logic ‘1’, the
SMBus host is reading data from the client device.
The PAC1710/20 SMBus address is determined by a
single resistor connected between ground and the
ADDR_SEL pin as shown in Table 5-1.
All SMBus Data bytes are sent most significant bit first
and composed of 8 bits of information.
5.0.3 SMBus ACK AND NACK BITS
The SMBus client will acknowledge all data bytes that it
receives (as well as the client address if it matches and
the ARA address if the ALERT
pin is asserted). This is
done by the client device pulling the SMBus Data line
low after the eigth bit of each byte that is transmitted.
The host will not acknowledge (NACK) the data
received from the client by holding the SMBus data line
high after the eigth data bit has been sent.
5.0.4 SMBus STOP BIT
The SMBus Stop bit is defined as a transition of the
SMBus Data line from a logic ‘0’ state to a logic ‘1’ state
while the SMBus clock line is in a logic ‘1’ state. When
the PAC1710/20 detects an SMBus Stop bit, and it has
been communicating with the SMBus protocol, it will
reset its client interface and prepare to receive further
communications.
5.0.5 SMBus TIMEOUT
The PAC1710/20 includes an SMBus timeout feature.
Following a 30 ms period of inactivity on the SMBus,
the device will time out and reset the SMBus interface.
The time-out functionality defaults to disabled and can
be enabled by writing to the TIMEOUT bit (see
Register 6-1).
5.1 SMBus and I
2
C Compliance
The major differences between SMBus and I
2
C
devices are highlighted below. For more information,
refer to the SMBus 2.0 and I
2
C specifications.
• PAC1710/20 supports I
2
C fast mode at 400 kHz.
This covers the SMBus maximum time of 100 kHz.
• Minimum frequency for SMBus communications
is 10 kHz.
• The SMBus client protocol will reset if the clock is
held at a logic ‘0’ for longer than 30 ms. This time-
out functionality is disabled by default in the
PAC1710/20 and can be enabled by writing to the
TIMEOUT bit. I
2
C does not have a timeout.
• The SMBus client protocol will reset if both the
clock and data lines are held at a logic ‘1’ for
longer than 200 μs (idle condition). This function
is disabled by default in the PAC1710/20 and can
be enabled by setting the TIMEOUT bit. I
2
C does
not have an idle condition.
•I
2
C devices do not support the Alert Response
Address functionality (which is optional for SMBus).
•I
2
C devices support Block Read and Block Write
differently. I
2
C protocol allows for unlimited
number of bytes to be sent in either direction. The
SMBus protocol requires that an additional data
byte indicating number of bytes to read/write is
transmitted. The PAC1710/20 supports I
2
C
formatting only.
TABLE 5-1: ADDR_SEL RESISTOR
SETTING
RES
(5%)
SMBus Address
RES
(5%)
SMBus Address
0 1001_100(r/w) 1600 0101_000(r/w)
100 1001_101(r/w) 2000 0101_001(r/w)
180 1001_110(r/w) 2700 0101_010(r/w)
300 1001_111(r/w) 3600 0101_011(r/w)
430 1001_000(r/w) 5600 0101_100(r/w)
560 1001_001(r/w) 9100 0101_101(r/w)
750 1001_010(r/w) 20000 0101_110(r/w)
1270 1001_011(r/w) Open 0011_000(r/w)
