PAC1710/20
DS20005386B-page 34 2015-2016 Microchip Technology Inc.
REGISTER 6-17: CHANNEL 2 V
SENSE
HIGH-LIMIT REGISTER (ADDRESS 1AH)
R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
C2SH<7:0>
bit 7 bit 0
Legend:
R = Read bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit in unknown
bit 7-0 C2SH<7:0>: Two’s complement high-limit channel 2 V
SENSE
(PAC1720)
0100_000 = 1024
0010_0000 = 512
0001_0000 = 256
0000_1000 = 128
0000_0100 = 64
0000_0010 = 32
0000_0001 = 16
1111_1111 = -1
1000_000 = -1024
Unimplemented: Read as ‘0’ (PAC1710)
REGISTER 6-18: CHANNEL 1 V
SENSE
LOW-LIMIT REGISTER (ADDRESS 1BH)
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C1SL<7:0>
bit 7 bit 0
Legend:
R = Read bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit in unknown
bit 7-0 C1SL<7:0>: Two’s complement low-limit channel 1 V
SENSE
0100_000 = 1024
0010_0000 = 512
0001_0000 = 256
0000_1000 = 128
0000_0100 = 64
0000_0010 = 32
0000_0001 = 16
1111_1111 = -1
1000_000 = -1024
