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PAC1720-1-AIA-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
2015-2016 Microchip Technology Inc. DS20005386B-page 25
PAC1710/20
6.1 Read Multiple Data Bytes
When any measurement high-byte register is read
(V
SOURCE
or V
SENSE
), the corresponding low byte is
copied into an internal “shadow” register. The user is
free to read the low byte at any time and be guaranteed
that it will correspond to the previously read high byte.
Regardless if the low byte is read or not, reading from
the same high byte register again will automatically
refresh this stored low byte data.
6.2 Detailed Register Description
REGISTER 6-1: CONFIGURATION REGISTER (ADDRESS 00H)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CDEN MSKAL C2IDS C2VDS TOUT C1IDS C1VDS
bit 7 bit 0
Legend:
R = Read bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit in unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 CDEN: Enables the ALERT
pin to be asserted when the conversion cycle is finished.
1 = ALERT
pin will be asserted for 5 μs when the conversion cycle is finished.
0 = ALERT
pin is not masked. If any of the appropriate status bits are set, the ALERT pin will be asserted.
bit 5 MSKAL: Masks the ALERT pin from asserting due to out-of-limit conditions.
1 = ALERT
pin is masked. It will not be asserted for any interrupt condition. The Status Registers will
be updated normally.
0 = ALERT pin is not masked. It will be asserted for any interrupt condition not masked by
Register 6-4. The Status Registers will be updated normally.
bit 4 C2IDS: Disables the V
SENSE
measurement for channel 2 (PAC1720)
1 = The device is not measuring the sense voltage. It will update CH2 Sense Voltage Registers when
a One-Shot command is given.
0 = The device is measuring sense voltage for CH2
Unimplemented: Read as ‘0’ (PAC1710)
bit 3 C2VDS: Disables the V
SOURCE
measurement for channel 2 (PAC1720)
1 = The device is not measuring the Source voltage. It will update CH2 Source Voltage Registers
when a One-Shot command is given.
0 = The device is measuring Source voltage for CH2
Unimplemented: Read as ‘0’ (PAC1710)
bit 2 TOUT: Enables the time-out and idle reset functionality of the communications protocol (see
Section 5.0.5 “SMBus Timeout”).
1 = Time out enabled
0 = Time out disabled
bit 1 C1IDS: Disables the V
SENSE
measurement for channel 1
1 = The device is not measuring the sense voltage. It will update CH1 Sense Voltage Registers when
a One-Shot command is given.
0 = The device is measuring sense voltage for CH1
bit 0 C1VDS: Disables the V
SOURCE
measurement for channel 1
1 = The device is not measuring the Source voltage. It will update CH1 Source Voltage Registers
when a One-Shot command is given.
0 = The device is measuring source voltage for CH1
PAC1710/20
DS20005386B-page 26 2015-2016 Microchip Technology Inc.
REGISTER 6-2: CONVERSION RATE REGISTER (ADDRESS 01H)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1
— — — — — —CONV<1:0>
bit 7 bit 0
Legend:
R = Read bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit in unknown
bit 7-2 Unimplemented: Read as ‘0’
bit 1-0 CONV<1:0>: Determines the conversion rate as shown in Table 4-1.
00b = 1 Sample/Second
01b = 2 Samples/Second
01b = 4 Samples/Second
11b = Continuous
REGISTER 6-3: ONE-SHOT REGISTER (ADDRESS 02H)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OS<7:0>
bit 7 bit 0
Legend:
R = Read bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit in unknown
bit 7-0 OS<7:0>: When the device is in the Standby state, writing to the One-Shot Register will initiate a
conversion cycle and update all measurements.
REGISTER 6-4: CHANNEL MASK REGISTER (ADDRESS 03H)
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — C2VS C2VSR C1VS C1VSR
bit 7 bit 0
Legend:
R = Read bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit in unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3 C2VS: Masks the ALERT
pin from asserting when the channel 2 V
SENSE
value meets or exceeds the
high limit or drops below the low limit (PAC1720).
1 = The channel 2 V
SENSE
voltage measurement cannot cause the ALERT pin to be asserted (if enabled).
0 = The channel 2 V
SENSE
voltage measurement can cause the ALERT pin to be asserted (if enabled).
Unimplemented: Read as ‘0’ (PAC1710)
bit 2 C2VSR: Masks the ALERT
pin from asserting when the channel 2 V
SOURCE
value meets or exceeds
the high limit or drops below the low limit (PAC1720).
1 = The channel 2 V
SOURCE
voltage measurement cannot cause the ALERT pin to be asserted
(if enabled).
0 = The channel 2 V
SOURCE
voltage measurement can cause the ALERT pin to be asserted (if enabled).
Unimplemented: Read as ‘0’ (PAC1710)
2015-2016 Microchip Technology Inc. DS20005386B-page 27
PAC1710/20
bit 1 C1VS: Masks the ALERT pin from asserting when the channel 1 V
SENSE
value meets or exceeds the
high limit or drops below the low limit.
1 = The channel 1 V
SENSE
voltage measurement cannot cause the ALERT pin to be asserted
(if enabled).
0 = The channel 1 V
SENSE
voltage measurement can cause the ALERT pin to be asserted
(if enabled).
bit 0 C1VSR: Masks the ALERT
pin from asserting when the channel 1 V
SOURCE
value meets or exceeds
the high limit or drops below the low limit.
1 = The channel 1 V
SOURCE
voltage measurement cannot cause the ALERT pin to be asserted
(if enabled).
0 = The channel 1 V
SOURCE
voltage measurement can cause the ALERT pin to be asserted
(if enabled).
REGISTER 6-5: HIGH-LIMIT STATUS REGISTER (ADDRESS 04H)
RC-0 U-0 U-0 U-0 RC-0 RC-0 RC-0 RC-0
CVDN
— — — C2VSH C2VRH C1VSH C1VRH
bit 7 bit 0
Legend:
R = Read bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit in unknown
bit 7 CVDN: Indicates that the conversion cycle (see Section 4.2 “Conversion Cycle”) is complete. This
bit is cleared when read.
1 = Conversion complete
0 = Conversion not complete
bit 6-4 Unimplemented: Read as ‘0’
bit 3 C2VSH: This bit is set when the channel 2
V
SENSE
value meets or exceeds its programmed high limit
(PAC1720).
1 = The channel 2 V
SOURCE
voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal operation
Unimplemented: Read as ‘0’ (PAC1710)
bit 2 C2VRH: This bit is set when the channel 2 V
SOURCE
value meets or exceeds its programmed high limit
(PAC1720).
1 = The channel 2 V
SOURCE
voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal Operation
Unimplemented: Read as ‘0’ (PAC1710)
bit 1 C1VSH: This bit is set when the channel 1 V
SENSE
value meets or exceeds its programmed high limit.
1 = The channel 1 V
SENSE
voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal Operation
bit 0 C1VRH: This bit is set when the channel 1 V
SOURCE
value meets or exceeds its programmed high limit.
1 = The channel 1 V
SOURCE
voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal Operation
REGISTER 6-4: CHANNEL MASK REGISTER (ADDRESS 03H) (CONTINUED)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

PAC1720-1-AIA-TR

Mfr. #:
Buy PAC1720-1-AIA-TR
Manufacturer:
Microchip Technology
Description:
Current & Power Monitors & Regulators Single I2C/SMBus Current Sensor
Lifecycle:
New from this manufacturer.
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