PAC1710/20
DS20005386B-page 32 2015-2016 Microchip Technology Inc.
REGISTER 6-13: CHANNEL 2 VSOURCE RESULT REGISTER (ADDRESSES 13H AND 14H)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
C2VR<15:8>
bit 15 bit 8
R-0 R-0 R-0 U-0 U-0 U-0 U-0 U-0
C2VR<7:5>
— — — — —
bit 7 bit 0
Legend:
R = Read bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit in unknown
bit 15-5 C2VR<10:0>: These registers contain the most recent digitized value Channel 2 V
SOURCE
samples
(PAC1720).
400h = 20V
200h = 10V
100h = 5V
080h = 2.5V
040h = 1.25V
020h = 625 mV
010h = 312.5 mV
008h = 156.25 mV
004h = 78.125 mV
002h = 39.063 mV
001h = 19.531 mV
Unimplemented: Read as ‘0’ (PAC1710)
bit 4-0 Unimplemented: Read as ‘0’
REGISTER 6-14: CHANNEL 1 POWER RATIO REGISTER (ADDRESSES 15H AND 16H)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
C1P<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
C1P<7:0>
bit 7 bit 0
Legend:
R = Read bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit in unknown
bit 15-0 C1P<15:0>: These registers contain the most recent channel 1 Power ratio calculations. This is a
16-bit binary number representing a ratio based on Power FSR.
